Investigation of hot carrier transport in silicon permeable basetransistors

The effects of variations in the source to drain distance have been investigated for several highly doped Permeable Base Transistor (PBT) structures. A detailed study of the hot electron transport in these structures is presented using a 2-D self-consistent full band Monte Carlo (MC) simulation program. The PBT structures considered are the overgrown, etched source and etched drain PBT. Finally we have simulated a structure where both the source and the drain have been etched. All structures have a high doping level in the channel (10¹⁷ cm^-3) and are operating under a gate biasing far from the threshold voltage. The etched structure shows a larger increase in the unity current gain frequency (f_T) than the overgrown structure as the source to drain distance decreases. By optimizing the source to drain distance of the etched source PBT, the f _T can be increased by a factor of two. Our Monte Carlo result has been compared with an ordinary drift-diffusion (DD) model and a more advanced energy transport (ET) model. The difference between the MC and DD model is largest for the etched structures, while it is less significant for the overgrown structure. However, all structures considered in this work, long and short channel devices, show a larger dc current level in the MC model. This is related to the large electric field and high carrier temperature near the gate depletion region     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Properties of selectively doped heterostructure transistors incorporating a superlattice donor layer

We report on some salient features of an improved structure of selectively doped heterostructure transistor (SDHT) incorporating a short-period (30 Å) Al0.6Ga0.4As/n-GaAs superlattice donor layer. We show that this superlattice-SDHT (S²DHT) structure is a good candidate for both low-temperature packaged operation and room temperature applications. In addition to eliminating drain I-V distortion at low temperature, the device shows a threshold voltage shift from 300 K to 77 K of only ∼50 mV. The device also has high transconductance (∼250 mS/mm for 1-µm gate lengths at room temperature), larger voltage swing, and higher current driving capability than conventional SDHT's.     

A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (⩽600°C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm²/V-s and 6×10⁶ respectively     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

Improved lifetime of poly-Si TFTs with a self-alignedgate-overlapped LDD structure

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H₂ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation     

Refractory metal silicon device technology

Films 2000–5000 Å thick of Mo or W deposited over thin films of thermally grown SiO₂ are shown to be effective high temperature diffusion masks against both phosphorous and boron. These metal films may be precisely patterned and their diffusion masking properties can be used to define the source and drain regions of MOSFETs. In this manner, self-registered MOSFETs can be fabricated with a portion of the diffusion masking metal film acting as the gate electrode. Using P or B doped deposited glasses as diffusion sources, n or p channel enhancement mode MOSFETs were made by diffusion through the exposed thin SiO₂ film into p and n type Si to form source and drain junctions. Contact was subsequently made by etching holes through the oxide layers to the source and drain regions and to the refractory metal gate electrode buried within the oxide layers. These devices exhibit channel mobilities between 200 and 300 cm²/V-sec at gate voltages about 10 V above threshold. The stability of MOS structures processed in a similar manner has been measured. After being stressed at ±6 × 10⁵ V/cm and 250°C for 15 hr, these devices exhibited shifts in their C---V characteristics less than 200 mV.     

Development of a new self-aligning contact technology

A self-aligning contact process (SACMOS) for MOS/VLSI technology is described. A new technique involving submerged implant into the source and drain is employed. This enables the enhanced oxidation of the previously heavily doped polysilicon gate compared to the more lightly doped source and drain. The implant also provides the source and drain extensions. During oxidation, silicon nitride pads protect all contacts. A noncritical masking and etching stage is used to yield contacts. The process uses two extra masking stages to produce self-aligned contacts to the source, drain, and gate of MOS transistors, yielding a significant reduction in the area required for contact regions and hence a greater packing density. A process verification chip illustrated that discrete transistors designed using the new process exhibited similar properties to conventionally designed devices. Also a 21-stage ring oscillator designed with a minimum dimension of 6 µm occupied 15 percent less space than a conventional device and operated at the same speed under similar bias conditions. Finally it is estimated that a ROM designed using the new process occupies 25 percent less space.     

A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson–SchrÖdinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry and device architecture can be considered. The investigation of short channel effects for different gate configurations and geometry parameters shows that double-gate devices offer quasi-ideal subthreshold slope and drain-induced barrier lowering without extremely thin gate dielectrics. Exploration of devices with parallel CNTs shows that on currents per unit width can be significantly larger than the silicon counterpart, while high-frequency performance is very promising.     

High-performance and low-cost 0.15-/spl mu/m nMOSFETs using simultaneous N-gate and source/drain doping process

A fabrication method for high performance and low cost nMOSFETs suitable for 0.15 and sub-0.15 /spl mu/m CMOS technology is proposed. In this method, n-poly gate doping prior to the definition of gate poly was skipped, i.e., gate poly is simultaneously doped by the source/drain ion implantation. Then, the source/drain implantation dose was increased by the amount used for gate pre-doping process. Although gate pre-doping is skipped, device performances such as device on-off current characteristics, active and poly sheet resistance and junction leakage current are compatible to the pre-doping ones. Moreover, the proposed method has the advantages of low cost and high yield because one mask step and several processes are reduced. The degree of active damage by the doubled source/drain implantation dose was investigated using the transmission electron microscopy, and high resolution x-ray diffraction spectroscopy.     

Submicrometer salicide CMOS devices with self-aligned shallow/deepjunctions

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5-μm physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

A low-temperature MOS LSI process

A low-temperature process is proposed for the fabrication of MOS LSIs with very small dimensions. Since this process needs no thermal treatment after gate insulation, shallow source/drain junction, ultra-thin gate oxide, and Al gate electrode can be used. The key processes are self-aligned gate pattern reversion using Mo dummy gates and ECR SiO₂ lift-off, and planarized Al gate electrode filling using resist/Al etch-back. Test devices fabricated to demonstrate the feasibility of this process operate without trouble     

Self-aligned metal-SiO2-InP based MISFETS having modulation doped channels

A novel metal-SiO₂-InP MISFET (metal-insulator-semiconductor field effect transistor) structure is proposed. This device incorporates a modulation doped channel and the self-aligned gate feature of Si MOSFETs. The modulation doping provides very high electron mobility and the self-alignment of gate, source and drain provides high packing density. Analytical results on current-voltage and transconductance characteristics are presented. Significant enhancement in high frequency performance over conventional MISFETs, employing SiO₂ as an insulator, is reported.     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

具有高掺杂表面层和阶梯栅结构SiC MESFETs双沟道器件研究

An improved dual-channel 4H-SiC MESFET with high doped n-type surface layer and step-gate structure is proposed, and the static and dynamic electrical performances are analyzed.A high doped n-type surface layer is applied to obtain a low source parasitic series resistance, while the step-gate structure is utilized to reduce the gate capacitance by the elimination of the depletion layer extension near the gate edge, thereby improving the RF characteristics and still maintaining a high breakdown voltage and a large drain current in comparison with the published SiC MESFETs with a dual-channel layer.Detailed numerical simulations demonstrate that the gate-to-drain capacitance, the gate-to-source capacitance, and the source parasitic series resistance of the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.     

An investigation of laser annealed and metal-induced crystallizedpolycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm²/Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of ~10¹⁹ cm^-3 which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.