Influence of defects in gate-oxide peripheral regions on the electrical characteristics of MOS structures

Radiation-induced defect formation is studied experimentally in the gate-insulator layer and at the semiconductor-insulator interface of NMOS and PMOS structures differing in perimeter-to-area ratio. The structures are fabricated by CMOS technology on the same n-Si wafer, the NMOS structures being formed in a p-well. Heavily phosphorus doped polysilicon and noncrystalline silicon dioxide are used as the gate and insulator materials, respectively. The devices considered are MOS varactors, MOS diodes, and MOSFETs. Capacitance-voltage characteristics are measured on the MOS varactors and diodes. The gate-voltage dependence is examined of surface conduction for the MOSFETs and the surface-recombination emitter-current component for the MOS diodes. The results are used to characterize defect formation in peripheral gate-oxide regions and the lightly doped part of the source (emitter) and the drain, as well as in the central gate-oxide region and at the Si/SiO₂ interface. The peripheral oxide regions are found to have a two-sided influence on the performance of the MOS structures. On the one hand, they act as a drain of uncombined hydrogen from the gate oxide, so that the effectiveness of defect deactivation by hydrogen depends on the perimeter-to-area ratio. On the other hand, the peripheral regions, particularly their corners, may have an elevated density of latent process-induced defects that can be activated by radiation, voltage, or thermal stress.     

Analytical equations for oscillation amplitude of MOS Colpitts oscillator

New analytical equations are presented for amplitude analysis of metal–oxide–semiconductor (MOS) Colpitts oscillator. These equations are obtained from a large signal analysis that includes MOS operation in the saturation, triode and cutoff regions. The analysis is based on a reasonable estimation for the output voltage waveform. The estimated waveform must satisfy the nonlinear differential equations governing the circuit. The validity of the proposed method and the resulting equations has been verified through simulations using TSMC 0.18?µm complementary MOS process. The results are also compared with the other methods. Simulation results show high validity of the proposed equations.     

MOS结构辐照陷阱消长研究的快速I—V技术

建立了一套用于MOS结构辐照陷阱消长规律研究的快速I－V在线测试系统，用此系统可进行自动加偏和Ids－Vgs亚阈曲线测试，从而可快速定性定量地获得辐照和退火环境中氧化物电荷和Si／SiO_2界面态随辐照剂量、时间、偏置等的依赖关系。快速I－V测试系统最高可以达到1次／秒的Ids－Vgs测量速度。用此系统研究了PMOSFET5×10~3Gy（Si）总剂量辐照后100℃恒温退火下，辐照陷阱的消长规律和机制。     

Accurate modeling and parameter extraction for MOS transistorsvalid up to 10 GHz

Accurate modeling and efficient parameter extraction of the small signal equivalent circuit of submicrometer MOS transistors for high-frequency operation are presented. The equivalent circuit is based on a quasi-static approximation which was found to be adequate in the gigahertz range if the extrinsic components are properly modeled. It includes the complete intrinsic quasi-static MOS model, the series resistances of gate, source, and drain, and a substrate coupling network. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. The extracted results are physically meaningful and can be used to “de-embed” the extrinsic effects such as the substrate coupling within the device. Good agreement has been obtained between the simulation results of the equivalent circuit and measured data up to 10 GHz     

Identification and localisation of gate oxide weaknesses in n-MOS transistors through Fowler-Nordheim tunnelling and SPICE simulation

Analysis of the I/V characteristics after Fowler-Nordheim (F-N) injection of n-MOS transistors with weak source-drain overlap regions show the presence of an anomalous 'hump' SPICE simulations show that the same hump can arise in localised damage regions along the source-drain periphery, and that this is possibly in the bird's beak region. The results suggest that SPICE simulations and F-N injection can be used to study localised damage in MOS transistors.<>     

A novel two-dimensional MOS transistor for analog applications

In analog MOS integrated circuits, matching between transistors is a critical requirement because the circuit performance is determined by the device matching available. A new type of matched configuration is presented in this paper which utilizes the inherent 2-D geometry of an MOS transistor which was hitherto unexplored. This has been achieved by adding two more diffusion regions along the length of a normal MOS transistor. The characteristics of the device thus formed have been modeled in the linear region for different configurations, by solving the 2-D current continuity equation. For the saturation region, an empirical relation has been given. Theoretical and experimental results for a test chip have been presented. A few potential applications are mentioned.     

A unified submicrometer MOS transistor charge/capacitance model formixed-signal IC's

A unified modeling approach for the submicrometer MOS transistor charge/capacitance characteristics in all operation regions is presented. Development of this MOS charge model is based on the charge-density approximation to reduce the complexity of the analytical expression. To model the charge density more accurately, the conductance-degradation coefficient is determined by the derivative of drain-to-source saturation voltage with respect to gate-to-channel potential. The unified charge densities in gate, channel, and bulk regions are obtained with the assistance of the sigmoid, hyperbola, and exponential interpolation techniques. Good agreement between the measurement data and simulation results is obtained     

磁敏MOS器件数值模拟及设计优化

本文对磁敏MOS器件进行了计算机模拟,提出用分区域方法进行器件的两维数值分析,有效地降低了计算费用.井利用BFGS方法,对磁敏MOS 器件进行了优化设计,分析结果表明,宽长比W/L为0.82的磁敏器件有最高的灵敏度,实验结果证实了这一理论预测.     

A compact model for flicker noise in MOS transistors for analog circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.     

A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.     

Theory of the surface depletion region for semiconductors with linearly graded impurity profiles

The theory of the surface depletion region for a semiconductor with a linearly graded impurity profile is described in this paper. Using the depletion approximation, expressions for the electric field, potential and surface potential are derived as functions of the profile parameters. The theoretical high frequency CV characteristics of an MOS structure built on such a surface are generated and compared with the experimental results obtained on MOS capacitors fabricated on implanted surfaces. The agreement between the theory and experimental results is very good. Since many diffused and implanted profiles can be approximated by piecewise-linear segments, the theory presented here can be extended and used in the modelling and simulation of a variety of ion-implanted MOS structures.     

Boron channel-stop design for poly-buffered LOCOS using selectiveboron segregation

A boron channel-stop compensation technique using a selective polysilicon etch prior to field oxidation is proposed for CMOS isolation technologies which use polysilicon buffered LOCOS. The stress relief polysilicon layer is selectively removed over the n-well field regions which results in additional boron segregation into the growing field oxide while the polysilicon layer is being oxidized over the p-well field regions. The resulting field threshold voltages are increased by as much as 11.6 and 6.4 V for the p-well and n-well MOS capacitors, respectively     

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.     

Reliability issues of scaled-down MOS transistors for gigabit circuits

The basic reliability issues of very small MOS transistors are addressed in this review and reliability constraints, such as trap-assisted tunneling, current increase at corner regions, oxide stability, oxide damage during processing, and hot carrier degradation are discussed. No major problems are expected for MOS transistors scaled down to their physical limits.     

模电教学中BJT与MOS的近似性分析

BJT 与MOS器件及电路是模电重要内容；教学中二者的电路模型与分析方法不一致，学生困惑于两套不同的器件及电路知识。本文在遵循器件及电路工作原理的基础上，首次将二者在小信号模型、电路参数、I-V方程、特性曲线、工作区间、指标计算上进行完整的近似性分析及一致性推导；在二者电路计算中，用三种单管单级放大器实例，阐述近似分析方法的便利性。本文是模电教学的有力补充。     

An MOS transistor model for analog circuit design

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model     

6H－SiC MOS结构电特性及其辐照效应的研究

对SiC MOS结构辐照引起的电参数退化及其电特性进行了研究。结果说明:在氧化层电场较高时Fowler-Nordheim隧穿电流决定着SiC MOS结构的漏电流,当幅照栅偏压为高的正电压时,电离幅照对SiC MOS电容的影响会更明显,SiC MOS器件比Si器件具有好的抗辐照的能力,在58kGy(Si)的辐照剂量下,其平带电压漂移不超过2V。     

Electric fatigue in MOS structures due to lowering of the potential barrier during the field ionization of insulator atoms

The influence of the ionized charge in an insulator on the excess current in an MOS structure is calculated. A comparison of numerical simulation results and experimental data shows that this effect can be responsible for a time-dependent breakdown of an ultrathin gate oxide in MOS transistors.     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Activation energy determination from low-temperature CV dispersion[semiconductor devices]

The response of semiconductor devices at low temperatures to changes in the voltage across the depletion region is limited by the dielectric relaxation time of the majority carriers in the bulk region. This results in a dispersion of the C-V curves at low temperatures. In this paper, we report a study of the dispersion seen in the accumulation and depletion regions of the C-V curve in n- and p-channel MOS transistors as well as in reverse biased one-sided abrupt junctions. From the admittance measured as a function of temperature and frequency, the dopant energy level is determined. The values of the activation energy measured using the diodes agree well with the corresponding values obtained using MOS devices