单位元波开关电容滤波器的新实现

本文给出了实现单位元波开关电容滤波器适配器的几个新电路。这些新适配器电路仪用一个单位增益器和一个两相时钟信号,而且电路特性对主寄生电容效应极不敏感。文中还分析了次寄生电容(包括电容器上极板对衬底的寄生电容和开关的寄生电容)对电路特性的影响。分析表明,整个次寄生电容效应表现为对反射系数的影响。通过调整一个电容,就可以把这种本来就很小的影响降至更小。另外,本文的电路还非常适合用于实现程控滤波器,可以有效地进行实时语声综合。最后,给出了一个五阶切比雪夫低通滤波器的例子。实验结果与理论相符。     

An integrated seventh-order unit element filter in VIS-SC technique

Describes a seventh-order unit element switched-capacitor filter based on the voltage invertor switches-switched capacitor (VIS-SC) concept. The operation of this filter is described in detail. It is shown that the effect of parasitic bottom plate capacitances can be overcome by using a special type of VIS. The influence of the top plate parasitics on the filter properties is discussed. Experimental results of an integrated NMOS version are given.     

NOVEL LINEAR TRANSFORMATION SWITCHED-CAPACITOR FILTER DESIGN

This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS filters.De-signed examples are given here.An Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic capacitances.The experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.     

New realization of inductances for switched-capacitor filters using voltage inverter switches

This paper describes a new design method of inductance simulation for switched-capacitor (SC) filters based on the VIS-SC concept. The resulting circuits have not only the excellent sensitivity behavior of VIS-SC filters, but also the low sensitivity to the main parasitics occuring in the MOS integrated circuit, i.e., the parasitic capacitances between the bottom plates of the implemented capacitors and substrate. As examples, a sixth-order band-pass and a sixth-order band-stop elliptic filter transformed from a third-order low-pass are given. Experimental results agree very well with theory. A brief analysis is given of certain parasitic effects in band-stop filters at the Nyquist frequency.     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

Current-Mode First-Order Allpass Filter Employing Single Current Operational Amplifier

A current-mode first-order allpass filter configuration is proposed. The presented circuit uses a single current operational amplifier (COA), a resistor and a capacitor, which are of minimum number. High output impedance of the proposed filter enables the circuit to be cascaded without additional buffers. The proposed circuit is insensitive to parasitic input capacitances and input resistances due to internally grounded input terminals of COA. It does not impose any component matching constraint in analog signal processing circuits. Non-ideal effects of COA to the first-order allpass network are also investigated. To demonstrate the performance of the proposed filter a new current-mode quadrature oscillator is given as an application example. The theoretical results are verified with PSPICE simulations using a new realization of fully differential CMOS COA.     

Switched-capacitor bandpass filter based on simulation of canonical reactance sections

A design method is described for switched-capacitor filters. It is based on the simulation of doubly terminated reactance filters in a canonical tandem section configuration and using the bilinear s-to-z transformation between the frequency planes of the continuous-time reference filter and the discrete-time switched-capacitor filter. The switched-capacitor circuits are completely insensitive to parasitic capacitances. The method permits the switched-capacitor realization of the whole class of lossless two-ports.     

Realization of High-Order OTRA-MOSFET-C Active Filters

High-order linear transformation (LT) MOSFET-C active filters with reduced parasitic capacitance effects based on operational transresistance amplifiers (OTRAs) are presented in this paper. A systematic method is developed to realize voltage-mode LT OTRA-based filters efficiently. Based on the proposed design procedures, we can synthesize high-order filters with OTRAs with only MOSFET resistor circuits (MRCs) and virtual grounded capacitors. Signal processing circuits employing OTRAs have almost constant bandwidths because of the use of current-feedback configurations. A third-order Chebychev lowpass filter is demonstrated. HSPICE simulation results that confirm the theoretical analysis are obtained. Furthermore, the proposed circuits can be extended to higher-order filters.     

Stray-insensitive differential input stages for A/D convertors

Novel input stages are proposed for A/D convertors. The circuits can accept differential input signals without sample-and-hold buffers, and are immune to the effects of parasitic capacitances.     

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.     

Current mode filters with reduced complexity using a single EX-CCCII

In this paper an active element Extra-X current controlled conveyor (EX-CCCII) is used to reduce the complexity of some existing circuits. Two second-order current-mode biquadratic filter circuits are proposed, each using a single active element and two grounded capacitors. The first circuit is three input single output (TISO) and the second one is single input three outputs (SITO) biquadratic filter. The First circuit can realize all the standard filter transfer functions, while the second circuit can realize LP, BP and HP responses. The study of non-idealities and parasitics of the active element and their effects on transfer functions is carried out. The new circuits are found to be simpler than the earlier ones in terms of number of transistors. The functionality of the proposed biquadratic filters is verified through detailed PSPICE simulations using 0.25 µm TSMC CMOS technology parameters.     

The effects of parasitic capacitance on the noise figure of MESFETs

The parasitic capacitance due to the gate pad and the gate feed area of a MESFET plays an important role in the low-noise performance of the device. Its effects on the noise figure have been measured and analyzed for π-FET device geometries. It is shown that there is an optimum unit gate width for the minimum noise figure. This optimum unit gate width depends on the device structure and the processing parameters. When the effects of parasitic capacitances are included, H. Fukui's (1979) equation predicts noise figures that are in good agreement with the experimental data     

A low-power multi-mode and multi-output high-order CMOS universal Gm-C filter

This paper presents a new CMOS high-order Gm-C universal filter which can realize multi-mode (current, voltage, trans-resistance and trans-conductance) filtering functions, using grounded capacitors to absorbing shunt parasitic capacitances and a reduced number of active elements which leads to the minimum chip size and power consumption. Furthermore, in current-mode implementation, the proposed circuit produces simultaneously multiple filtering functions while uses just one configuration of inputs. Also, as the result of sensitivity analysis shows, the new filter structure has a very low sensitivity to the values of capacitors and trans-conductance elements. However, the proposed Gm-C filter is designed and simulated in HSPICE using 0.18 μm CMOS technology parameters and HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB which justifies the design accuracy and low-power, multi-mode, multi-output universal filtering performance of the proposed circuit.     

A New RF CMOS Gilbert Mixer With Improved Noise Figure and Linearity

The noise figure of an RF CMOS mixer is strongly affected by flicker noise. The noise figure can be improved using pMOS switch circuits, which insert current at the on/off crossing instants of the local oscillator switch stage because the circuits reduce the flicker noise injection. When it is applied to a conventional Gilbert mixer, the injection efficiency and linearity are degraded by the nonlinear parasitic capacitances of the pMOS switch circuits and the leakage through the parasitic path. We propose the pMOS switch circuits with an inductor, which tunes out the parasitic components at 2f_o and closes out the leakage path. The mixer fabricated in 0.13-mum CMOS at 2.4-GHz center frequency has provided improved characteristics for linearity and noise figure.     

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1 V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18 µm TSMC technology parameters to verify the feasibility of the filter circuit.     

Automated hierarchical CMOS analog circuit stack generation withintramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples     

Coupled Rectangular Bars Between Parallel Plates

Curves are presented giving the even-mode fringing capacitance, the odd-mode fringing capacitance, and the difference between odd- and even-mode fringing capacitances for wide ranges of thickness and spacing of rectangular bars centered between parallel plates. Simple formulas are given relating these capacitances to even- and odd-mode characteristic impedances of coupled rectangular bars. possible applications to strip-line and other circuits are described. The appendix gives the derivation of the fringing, capacitances by conformal mapping techniques. The results are exact for bars extending in width infinitely far from the coupling region, and have only small error (less than 1.24 per cent) for bars whose width is greater than about 35 per cent of the difference between plate spacing and bar thickness.     

On the frequency limitations of the circuits based on second generation current conveyors

An equivalent circuit for the translinear implementation of the second generation current conveyors with positive or negative current transfer is given. This circuit takes into account the various parasitic elements of the conveyor which induce frequency limitations (gain values, poles of the transfers, and parasitic impedances). The methods allowing the determination of the values for these parasitic elements are indicated and discussed. The effect of each element on the frequency responses of the circuits using the conveyors are studied in every detail. The frequency behavior of two circuits are analyzed as examples: a voltage amplifier without feedback and two configurations for a second order biquad filter operating in current-mode. All the theoretical results of the analysis are well confirmed from SPICE simulations.     

对寄生电容不灵敏的开关电容有源滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭圆低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

Automated synthesis of passive filter circuits including parasitic effects by genetic programming

In this paper, we propose a genetic programing method to synthesize passive filter circuits including parasitic effects, which are very common in high-frequency application. This approach allows circuit topology and component values to be evolved simultaneously; therefore, novel circuits different from those generated by traditional methods can be explored. Experimental results show the proposed method can effectively generate not only compliant but also efficient solutions of such problems where the traditional approaches fail.