Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Circuit emulation service (CES) allows time‐division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase‐locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd.     

Iterative detection of turbo-coded offset QPSK in the presence of frequency and clock offsets and AWGN

The key contribution of this paper is to develop transmitter and receiver algorithms in discrete-time for turbo-coded offset QPSK signals. The procedure for simulating a clock offset between the transmitter and receiver is described. Due to the use of up-sampling, matched filtering and a differential correlation approach at the receiver, the time required for detecting the start of frame (SoF) is just around 500 symbols, which is also the length of the preamble. The initial estimate of the SoF and the frequency offset, obtained using the differential correlation approach, is improved using an iterative process. A novel two-step maximum likelihood (ML) frequency offset estimation is proposed, which significantly reduces the complexity over the conventional ML estimation. The decision-directed carrier and timing recovery algorithms use simple first-order IIR filters to track the carrier phase and clock slip. The proposed synchronization and detection techniques perform effectively at an SNR per bit close to 1.5?dB, in the presence of a frequency offset as large as 30% of the symbol-rate and a clock offset of 25?ppm (parts per million). It is shown via simulations that the performance loss with respect to the bare turbo code is only about 0.5?dB, for a preamble length of 500 and a BER of 10^?7. The proposed techniques are well suited for software implementation.     

OFDM系统中同步问题的研究

OFDM系统的实现还存在着一些方面问题,如：同步问题尤其是频偏,峰值功率与平均功率比值过高,器件的非线性化等。OFDM系统对同步偏差敏感是本文讨论的重点,尤其是频偏。因此怎样获得准确的符号定时和载波频偏估计对OFDM系统性能至关重要。本文围绕OFDM同步过程中的符号定时和载波频率偏差问题进行描述,在分别介绍同步过程中捕获和跟踪两个阶段各自一些典型算法基础上,对一种基于保护间隔／循环前缀（PI／CP）的联合实现符号定时和载波同步最大似然估计（MLE）算法进行叙述并仿真。     

Clock synchronization using a linear process model

In this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least‐squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals. Copyright © 2006 John Wiley & Sons, Ltd.     

Pilot-aided sampling frequency offset estimation and compensation using DSP technique in DD-OOFDM systems

To improve the outage performance of an optical orthogonal frequency-division multiplexing (OFDM) system under the frequency offset between the sampling clocks in the transmitter and receiver, a pilot-aided sampling frequency offset (SFO) estimation and compensation scheme for the optical OFDM system with intensity-modulation and direct-detection (DD-OOFDM) is experimentally demonstrated. The experimental and simulated results show that the scheme can work effectively even with large sampling frequency offsets. In addition, it can achieve a good bit error rate (BER) performance without the sampling clock frequency synchronization in the receiver.     

运动误差对双站SAR相位同步及成像的影响

收、发系统间的相位同步是双站合成孔径雷达的一项关键技术,采用锁相环接收机是实现双站SAR系统相位同步的一种可能方法.本文主要就锁相环接收机在运动误差条件下的相位同步问题进行了研究,并分析了锁相环相位误差对系统成像的影响,最后,给出了计算机仿真结果.     

Communication systems with PPM signaling

Effect of imperfect slot synchronization between the transmitter and the receiver on optical synchronous code-division multiple-access (CDMA) systems using pulse position modulation as data modulation (PPM/CDMA) is investigated. Optical orthogonal codes (OOC's) are employed as signature sequences, and parallel optic-fiber delay line encoders and correlators are adopted in the transmitters and the receivers, respectively. The upper bound on the bit error probability of PPM/CDMA is derived under the condition that the receiver slot timing shifts from the transmitter timing clock. The bit error probability performance is evaluated for some values of the number of slots per frame, average signal photocount, and the number of simultaneous users. It is shown that as the number of slots per frame increases, the timing offset should be restricted to be smaller to achieve low bit error probability. Further, when the timing offset is small, the improvement of the bit error probability performance with the increase of the number of slots per frame under the photocount per second constraint is shown to be larger than that under the photocount per symbol constraint     

DSSS接收机中PN码同步的FPGA实现

PN码同步是直接序列扩频通信系统实现正确解调的首要条件,由于发送端和接收端的时钟不同所造成的码片相位偏移将影响到传输数据的正确接收,因此根据PN码良好的自相关特性,提出了一种在基带数字信号处理中基于FPGA的能有效锁定发送端和接收端时钟,实现PN码同步的方案。并结合系统框图具体分析了同步捕获和跟踪中各个模块的功能和实现方法,跟踪模块中涉及到模拟电路部分的也给出了具体的电路设计,最后说明了调试过程中的一些问题及解决技巧。     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

Design of tracking loop with dirty templates for UWB communication systems

Maintaining satisfactory synchronization between transmitter and receiver is one of the major challenges in carrying out highly efficient ultra-wideband (UWB) communications. For tracking purposes, the delay-locked loop (DLL) concept is applied. The DLL could be considered as a fundamental tracking technique for UWB devices. In this paper, the reference signal is generated at the receiver based on an approach called timing with dirty template. This approach promises to improve tracking performance while reducing receiver structure complexity. After the reference template is generated, we derive first-order and second-order DLL designs for UWB systems. Furthermore, we utilize the benefits of time-hopping codes to enhance noise handling ability of the DLL. Finally, the parameters of the proposed DLL will be selected to optimize tracking behavior in the presence of the ambient noise and Doppler effects. Simulation results show tracking performance across various DLL parameter values.     

Some improved and generalized estimation schemes for clock synchronization of listening nodes in wireless sensor networks

A sender-receiver paradigm, in which a master and slave node exchange timing packets to estimate the clock offsets of the slave node and other nodes located in the common broadcast region of master and slave nodes, is adopted herein for synchronizing the clocks of individual nodes in a wireless sensor network (WSN). The maximum likelihood estimate of the clock offset of the listening node hearing the broadcasts from both the master and slave nodes was derived in [1] assuming symmetric exponential link delays. This paper advances those results in two directions. First, some improved estimators, each being optimal in its own class, are derived for the clock offset of the listening node and mean link delays. Second, the results are generalized by addressing the more realistic problem of clock offset estimation under asymmetric exponential delays. The results presented in this paper are important for time synchronization of WSNs, where these techniques can be utilized to achieve accurate clock estimates with reduced power consumption.     

Novel system clock generation from a modulated signal

This paper describes a novel technique to derive a pure-spectral system clock with a common multi-modulus divider from a frequency modulated signal. Therefore, the dividing factor is inverse frequency modulated to compensate the frequency modulation component on the divider input signal. Additionally, $\Upsigma\Updelta$ dithering is applied to the frequency divider. The technique is used for a FM-radio transmitter based on an all-digital phase-locked loop (PLL) to generate a higher-frequency clock for baseband signal processing. It can also be applied to other PLL based transmitters or receivers, especially, if only a slow PLL reference clock is available and a faster system or baseband clock is required. The main factor determining the quality of the generated clock signal is the PLL??s reference quartz oscillator as it determines the accuracy of the PLL??s RF oscillator, which limits then the accuracy of the newly generated clock. In the FM-radio transmitter, a generated ??1?MHz clock signal with 30.58?ppm frequency offset and 515?ps root mean square jitter is generated. The phase noise is determined to ?83.5?dBc/Hz at 10?kHz offset and ?70.5?dBc/Hz at 1?kHz, respectively. The signal can also be used in co-integrated or external circuits.     

Symbol synchronization technique in COFDM systems

In this paper we focus our research on the symbol timing synchronization technique in COFDM systems. A new method utilizing pilots to do coarse symbol timing is proposed. It overcomes the problem of fluctuation of the estimated symbol start position with cyclic prefix correlation method. The symbol timing error with the proposed method is within only /spl plusmn/10 samples. Different from previous algorithms in , we utilize the known pilot information to estimate the residual symbol timing offset with low system complexity. This paper also proposes a new control model for the sampling clock adjustment, different from the phase-locked loop (PLL), or delay-locked loop (DLL) method. The simulation and correspondent Field Programmable Gate Array (FPGA) circuit through test in HDTV prototype in Team of Engineering Expert Group (TEEG) proves its feasibility and availability. The proposed method is also suitable for burst mode transmission systems such as Wireless Local Area Network (WLAN) and Fixed-Broadband Wireless Access (F-BWA).     

一种基于训练序列的改进的OFDM同步算法

文章在研究S&C算法和Park算法的基础上,提出一种基于训练序列的改进的正交频分复用(OFDM)同步算法.改进后的算法只使用一个训练符号,并通过对训练符号在时域乘以差分序列来消除定时同步中的峰值平台问题,通过对接收端和发射端的训练符号在频域的自相关性来估计载波整数倍频偏.改进后的算法在定时同步和载波频偏的纠正上较S&C算法有了较大的提高.     

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of-99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.     

一种改进的GFDM时频同步算法

针对广义频分复用( GFDM)系统对符号定时同步要求较高的问题,提出了一种新的基于前缀码的同步算法。在接收端,在获取粗略定时信息的基础上,利用前缀码前后两部分的相位差实现载波频偏估计,并对接收序列的频率偏移进行纠正,然后通过纠正后序列与已知发射前缀的互相关函数实现精确的符号定时估计。由于该前缀码具有共轭对称的特性,使其避免了“平顶效应”的出现。结合5G中低时延高可靠场景,在频率选择性信道中对其进行仿真,并通过均方误差对其性能进行了评估。理论分析及仿真结果表明,该算法相对于原算法具有更好的定时同步性能和更低的复杂度,提升了GFDM系统的整体性能。     

单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

针对单光子探测盖革雪崩焦平面读出电路应用,基于全局共享延迟锁相环和2维H型时钟树网络,该文设计一款低抖动多相位时钟电路。延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块,引入差分电荷泵结构,减小充放电流失配,降低时钟抖动。采用H时钟树结构,减小大规模电路芯片传输路径不对称引起的相位差异,确保多路分相时钟等延迟到达像素单元。采用0.18 μm CMOS工艺流片,测试结果表明,延迟锁相环锁定频率范围150～400 MHz。锁定范围内,相位噪声低于–127 dBc/Hz@1 MHz,时钟RMS抖动低于2.5 ps,静态相位误差低于65 ps。     

MIMO-OFDM系统训练序列构造及其同步方法

针对MIMO-OFDM系统对同步错误率和载波频偏特别敏感问题,本文提出了MIMO-OFDM系统训练序列构造及其同步方法.该同步方法设计的训练序列由两个结构不同的序列构成：第一个序列利用重复性构成,第二个序列利用反对称性构成,其构造训练序列中的β因子影响系统定时同步性能.在接收端,利用训练序列和本地数据信号进行互相关获取定时同步,在获取精确地定时同步后进行小数频偏估计和整数频偏估计,其整数频偏估计范围可达到1/4带宽.通过理论分析和仿真表明：本文提出的同步新方法比常规方法有更好的同步性能,并且降低了系统计算复杂度.     

Synchronization for IR‐UWB System Using a Switching Phase Detector‐Based Impulse Phase‐Locked Loop

Conventional synchronization algorithms for impulse radio require high‐speed sampling and a precise local clock. Here, a phase‐locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one‐tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high‐speed ultra‐wideband transceiver shows its feasibility, low complexity, and high precision.     

Timing recovery for OFDM transmission

Orthogonal frequency division multiplexing (OFDM) is an effective modulation technique for high-rate and high-speed transmission over frequency selective fading channels. However, OFDM systems can be extremely sensitive and vulnerable to synchronization errors. In this paper, we present a scheme for performing timing recovery that includes symbol synchronization and sampling clock synchronization in OFDM systems. The scheme is based on pilot subcarriers. In the scheme, we use a path time delay estimation method to improve the accuracy of the correlation-based symbol synchronization methods, and use a delay-locked loop (DLL) to do the sampling clock synchronization. It is shown that by using this scheme, the mean square values of the symbol timing estimation error can be decreased by several orders of magnitude compared to the common correlation methods in both the AWGN and multipath fading channels. In addition, the scheme can track the symbol timing drift caused by the sampling clock frequency offsets