一种可实现STDP机制的CMOS突触和神经元电路设计

设计了一个高度集成的、高能效的CMOS突触和神经元电路。该突触电路可以实现基于脉冲时间依赖可塑性(Spike Timing Dependent Plasticity,STDP)的学习机制。通过这种机制可以模拟动作脉冲在真实突触中的传导特性并大规模集成为神经形态芯片。该电路采用低功耗的设计方法,晶体管偏置在亚阈值区,由低压电源(0.6 V)供电,采用0.18μm标准CMOS工艺实现。仿真结果表明,突触权值的变化为0.17 V~0.43 V;神经元电路可以真实模拟出神经元放电的多种模式,如RS(Regular Spike)模式、LTS(Low-Threshold Spike)模式、CH(Chattering)模式和IB(Intrinsic Bursting)模式等,电路在产生动作电位时每个脉冲平均仅消耗约0.6 p J的能量。     

基于忆容桥的突触电路研究

利用4个相同忆容器构建一个能实现零、正和负突触权重的忆容桥电路。在附加3个晶体三极管后,忆容桥权重电路能够实现神经细胞的突触操作。由于整个操作都是基于脉冲输入信号,因此整个电路是高效节能的。通过Matlab实现突触权重设计和突触权重乘法的模拟。仿真实验结果表明,基于线性忆容桥的突触电路在性能上与忆阻突触桥电路基本相当,优于传统突触乘法电路。     

模拟电路实现的神经元控制器的仿真研究

该文研究一种适用于电动机控制的模拟电路实现的神经元自适应控制器。根据神经元的特性,将数字神经元控制器模拟化,获得模拟神经元控制器。该文还研究用MATLAB中的动态仿真工具SIMULINK对其进行仿真的方法。仿真结果表明模拟电路实现的神经元控制器比模拟PID具有更良好控制特性,并实现神经元权值的自动调节。该仿真方法为用电路仿真软件进行电路设计、仿真以及实际电路的实现打下良好的基础,提高设计效率。     

人工神经网络VLSI脉冲流算法实现技术

人工神经网络以其自组织、自适应、自学习能力以及非线性、非局域性、非定常性和凸性等优点得到广泛重视。本文分析现有人工神经网络模型及算法,总结了现有人工神经网络实现上的弊端,然后着重讨论了数据模结合的VLSI人工神经网络技术和脉冲流技术。在现有的各种脉冲流技术基础上,给出一个以模拟方式实现突触乘积和突触输出累加,数字方式实现权值储存的脉冲流人工神经网络。     

基于FPGA的晶闸管过零触发调功电路设计

本文针对传统的用模拟电路方法设计晶闸管过零触发脉冲电路的缺点,采用FPGA为核心.设计了一个8级功率可调的晶闸管过零触发电路,该电路包括三部分:过零脉冲产生;控制信号产生;负载触发脉冲产生.三相同步方波信号输入该电路后,将产生6路脉冲个数可调的过零触发信号,从而实现对负载功率的调节.文章采用Ouarts Ⅱ平台仿真,VHDL语言实现编程,电路简单实用,可靠性高.     

量化数字锁相环的改进

<正> 为加速海洋科研工作、近来为海上浮标设计了一台遥控指令接收机。接收等幅编码报、码元速率75波特,每次通讯前发射三秒左右同步信号,要求同步时间小于三秒,同步定位(相对)误差E<10%。本文只介绍同步信号提取电路及其改进。图1是同步信号提取环(量化数字锁相环)路方框图。由接收机来的等幅同步脉冲经放大、限幅、滤去干扰,经微分将其前沿负尖脉冲输出,经单稳S及倒相器形成以前沿定位的同步基准脉冲P_s加到鉴相器,同本机同步信号进行相位比较。两者不同步时产生相位误差信号,通过控制电路输出误差脉冲及加、减法指令到数字滤波器(可逆计数器),使计数器在本机同     

基于Temporal rule的忆阻神经网络电路

忆阻器是一种动态特性的电阻,其阻值可以根据外场的变化而变化,并且在外场撤掉后能够保持原来的阻值,具有类似于生物神经突触连接强度的特性,可以用来存储突触权值。在此基础上,为了实现基于Temporal rule对IRIS数据集识别学习的功能,建立了以桥式忆阻器为突触的神经网络SPICE仿真电路。采用单个脉冲的编码方式,脉冲的时刻代表着数据信息,该神经网络电路由48个脉冲输入端口、144个突触、3个输出端口组成。基于Temporal rule学习规则对突触的权值修改,通过仿真该神经网络电路对IRIS数据集的分类正确率最高能达到93.33%,表明了此神经系统结构设计在类脑脉冲神经网络中的可用性。     

基于Proteus数字频率计的设计

该数字频率计主要由74系列集成电路组成,被测脉冲方波信号加入到信号输入端,由门控信号对经闸门电路的方波脉冲的个数进行计数,利用门控信号的下降沿经反相器去控制锁存器74273,将信号锁存,并用门控信号的低电平去给计数器清零。测试结果由锁存译码显示电路进行显示,达到了很好的显示效果,以此实现计数的功能。并通过Proteus仿真软件验证了设计的正确性。     

XCP调频波脉冲计数鉴频系统的FPGA实现

为提高XCP中三路调频信号鉴频解调的抗干扰性能,采用脉冲计数式鉴频解调法,鉴频中采用倍频技术,提高了鉴频灵敏度。由参考信号发生器产生正交CQR和同相CIR两个参考信号．利用这两个相互正交的同步信号,并行控制多路脉冲计数器实施数字鉴频。采用现场可编程逻辑门阵列FPGA进行鉴频器硬件电路设计来降低系统复杂度并提高系统稳定性。测试结果表明,系统完全满足精度及可靠性等方面要求。     

基于神经网络VLSI与噪声信号的故障诊断

为了改变传统的基于软件的机械故障诊断模式，以及发挥神经网络超大规模集成电路(vLSI)的优势，提出了一种用于故障诊断识别的脉冲频率调制(PFM)模拟神经网络脉冲流vLSI电路。实现了一种脉冲流数字模拟混合突触乘法／加法器电路，而且该神经网络电路的突触权值不需要学习调整．降低了电路的复杂性。以此电路为基础．设计了进行主轴承磨损故障诊断的神经网络故障识别系统。利用含有故障信息的噪声信号代替传感器安装困难的基于振动信号的特征值提取，最后．根据代表待识别信号与标准故障模板之间欧氏距离的电路输出端电容电压值可以判断出故障类别。该电路具有较高的识别精度．可以实现噪声故障信号的实时在线识别。     

Neuron-synapse IC chip-set for large-scale chaotic neural networks.

We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of the analog circuitry. We can digitally control most of the model parameters by means of programmable capacitive arrays embedded in the SC chaotic neuron chip. Since the output of the neuron is transfered into a digital pulse according to the all-or-nothing property of an axon, we design a synapse chip with digital circuits. We propose a memory-based synapse circuit architecture to achieve a rapid calculation of a vast number of weighted summations. Both of the SC neuron and the digital synapse circuits have been fabricated as IC forms. We have tested these IC chips extensively, and confirmed the functions and performance of the chip-set. The proposed neuron-synapse IC chip-set makes it possible to construct a scalable and reconfigurable large-scale chaotic neural network with 10000 neurons and 10000/sup 2/ synaptic connections.     

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

 Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against V _dd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.     

Pulse-stream VLSI neural networks mixing analog and digitaltechniques

The pulse-stream technique, which represents neural states as sequences of pulses, is reviewed. Several general issues are raised, and generic methods appraised, for pulsed encoding, arithmetic, and intercommunication schemes. Two contrasting synapse designs are presented and compared. The first is based on a fully analog computational form in which the only digital component is the signaling mechanism itself-asynchronous, pulse-rate encoded digital voltage pulses. In this circuit, multiplication occurs in the voltage/current domain. The second design uses more conventional digital memory for weight storage, with synapse circuits based on pulse stretching. Integrated circuits implementing up to 15000 analog, fully programmable synaptic connections are described. A demonstrator project is described in which a small robot localization network is implemented using asynchronous, analog, pulse-stream devices.     

Modular neuron comprises of memristor-based synapse

Design of analog modular neuron based on memristor is proposed here. Since neural networks are built by repetition of basic blocks that are called neurons, using modular neurons is essential for the neural network hardware. In this work modularity of the neuron is achieved through distributed neurons structure. Some major challenges in implementation of synaptic operation are weight programmability, weight multiplication by input signal and nonvolatile weight storage. Introduction of memristor bridge synapse addresses all of these challenges. The proposed neuron is a modular neuron based on distributed neuron structure which it uses the benefits of the memristor bridge synapse for synaptic operations. In order to test appropriate operation of the proposed neuron, it is used in a real-world application of neural network. Off-chip method is used to train the neural network. The results show 86.7 % correct classification and about 0.0695 mean square error for 4-5-3 neural network based on proposed modular neuron.

     

基于结构学习和迭代自映射的自联想记忆模型

传统的人工神经元网络连接结构是固定的,是对权值的学习.提出一种基于生理神经元特征的人工神经元模型,并在以此为单元构成的用于实现自联想记忆的神经网络上进行对结构的学习.学习算法以设定神经元的输入/输出感受野、调整突触和轴突末梢的连接、并行的自投影迭代为特征.给出了此网络模型的矩阵描述和实验结果.     

Two digital circuits for a fully parallel stochastic neural network

This paper presents two digital circuits that allow the implementation of a fully parallel stochastic Hopfield neural network (SHNN). In a parallel SHNN with n neurons, the n*n stochastic signals s (ij) pulse with probability which are proportional to the synapse inputs, are simultaneously available. The proposed circuits calculate the summation of the stochastic input pulses to neuron i(F(i)=Sigma(j) s(ij)). The resulting network achieves considerable speed up with respect to the previous network.     

An analog CMOS chip set for neural networks with arbitrarytopologies

An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4x4 matrix-vector multiplier with variable, 10-b resolution matrix elements. The propagation delay of the test chips was measured to 2.6 mus per layer.     

PWM型VLSI神经网络在故障诊断中的应用

An improved pulse width modulation (PWM) neural network VLSI circuit for fault diagnosis is presented, which differs from the software-based fault diagnosis approach and exploits the merits of neural network VLSI circuit. A simple synapse multiplier is introduced, which has high precision, large linear range and less switching noise effects. A voltage-mode sigmoid circuit with adjustable gain is introduced for realization of different neuron activation functions. A voltage-pulse conversion circuit required for PWM is also introduced, which has high conversion precision and linearity. These 3 circuits are used to design a PWM VLSI neural network circuit to solve noise fault diagnosis for a main bearing. It can classify the fault samples directly. After signal processing, feature extraction and neural network computation for the analog noise signals including fault information, each output capacitor voltage value of VLSI circuit can be obtained, which represents Euclid distance between the corresponding fault signal template and the diagnosing signal, The real-time online recognition of noise fault signal can also be realized.     

A scalable optoelectronic neural system using free-space opticalinterconnects

The design of a scalable, fully connected 3-D optoelectronic neural system that uses free-space optical interconnects with silicon-VLSI-based hybrid optoelectronic circuits is proposed. The system design uses a hardware-efficient combination of pulsewidth-modulating optoelectronic neurons and pulse-amplitude-modulating electronic synapses. Low-area, high-linear-dynamic-range analog synapse and neuron circuits are proposed. SPICE circuit simulations and an experimental demonstration of the free-space optical interconnection system are included.