一种VLSI设计到无向赋权图的转换系统

基于VLSI剖分问题的需要,设计并实现了VLSI设计到无向赋权图的转换系统(VLSI/Graph Converter,VGC).介绍了电路构造图和图文件存储格式,给出了VGC的处理流程图,提出了针对VLSI线网的无向赋权图转换算法.该算法解决的关键问题是,遍历树状结构的VLSI线网,将其转换为无向赋权图并存储为指定的图文件格式.VGC系统在Windows平台下用C++实现.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU转换为无向赋权图,避免了直接在VLSI线网上进行剖分,提高了VLSI剖分的效率.     

基于层次式有向超图模型的胚胎硬件功能描述转换方法

当前胚胎硬件的实际工程应用受到限制,原因在于其应用设计自动化程度低,功能分化主要由人工完成,导致大规模电路功能分化难以实现.基于大规模电路功能分化的需要,针对典型多层胚胎硬件结构,提出了胚胎硬件功能的层次式有向超图描述及其存储方式,开发了基于正则匹配的硬件语言描述到层次式有向超图的转换算法,从而有效地将胚胎硬件功能分化问题转换为不同粒度的超图划分问题.为了建立分粒度层次式有向超图模型,进而设计并实现了胚胎硬件的硬件语言描述到有向超图的转换系统（Hypergraph For Embryonics, HGFE）.实验及分析表明,该系统适用于几十门至几万门的测试电路,为胚胎硬件功能分化提供了良好的图论模型,并和有向无环图对比,建模时间减少了至少28.7%,存储空间减少了至少30.1%,验证了该方法的优越性.     

一种ISPD98电路网表到超图的转换算法

以电路测试基准ISPD98的模型用例及对应的超图为例,阐述了ISPD98电路网表文件格式、超图的压缩存储格式和文件存储格式.提出了一种ISPD98电路网表到超图的转换算法.它读取ISPD98电路网表文件数据,将其映射到超图的压缩存储格式,并存储为指定的超图文件存储格式,从而有效地将电路划分问题转换为超图划分优化问题.实验表明,该转换算法能正确地将ISPD98电路网表转换为超图的文件存储格式,有效地避免了直接在ISPD98电路网表上进行划分,提高了电路划分的效率.     

JPEG2000中算术编码的VLSI结构设计

算术编码算法对于无损数据压缩是一种非常有效的方法,它已经被JPEG2000标准所采用.通过研究JPEG2000标准中的算术编码算法,设计了一种算术编码器的VLSI结构.该设计用Verilog语言进行了RTL级描述,然后用Modelsira对电路进行了仿真,经Quartus综合以后在FPGA上进行了验证.实验表明,在Ahera的芯片EP2C35F672C8上,该设计最高工作时钟可达63.37 MHz,可以作为IP核应用于JPEG2000图像编码芯片中.     

基于同步并行结构的视频处理IP模块的VLSI设计

本文在讨论隔行视频信号的逐行处理算法的VLSI实现和视频信号的色度处理和色度空间转换的硬件实现基础上,针对视频信号处理实时性,并发性以及运算量大的特点,提出了基于同步并行流水线的VLSI结构.同时结合SOC的IP模块设计给出相应的硬件实现算法.该设计已基于0.35μm CMOS工艺标准单元库进行了综合验证.     

多通道数字助听器算法及低功耗VLSI设计

改进了多通道数字助听器中的听力补偿和噪声消除算法,并进行了低功耗VLSI设计.听力补偿方面,提出一种改进的多通道宽动态范围压缩(WDRC)算法;该方法降低了存储和计算开销,并抑制了对残余背景噪音的过度放大.噪声消除方面,利用语音谱和噪声谱的帧间相关性,改进了传统的多子带谱相减算法,使之在硬件实现时便于并行运算,同时不影响消噪性能.最后,综合采用多种低功耗设计方法,在SMIC的130nm工艺条件下,完成了基于上述算法的多通道数字助听器VLSI设计.后仿结果表明,该设计总功耗仅为228μW.     

用于H.264/AVC的D级数据重用整数运动估计VLSI结构

本文提出了一种用于H.264/AVC的D级数据重用整数运动估计VLSI结构.提出的结构是在一种固定块尺寸运动估计VLSI结构基础上,利用交叉网络实现变块尺寸的计算,使用多bank的存储器组织方式,使片上存储器的读写规则简单,易于处理不同搜索范围和不同尺寸的视频的运动估计.提出的运动估计结构用Verilog HDL描述,使用HJTC 0.18μm工艺,用Synopsys DC做了逻辑综合.相比现有结构,该结构由于增加片上存储器,因此数据重用率高,大大降低了存储带宽需求;另外数据吞吐率高,能够满足高性能视频编码需求.     

一种三维小波序列图像编码算法及其FPGA实现

根据序列图像编码的特点。利用Harr小波变换、适合硬件实现的快速二维小波变换和快速零树编码算法,提出了一种适合硬件实现的三维小波变换序列图像编码算法。设计了该算法的VLSI结构,编写了相应的Verilog HDL模型,进行了仿真和逻辑综合,并用FPGA进行了验证。     

RNS与Delta-Sigma编码的位数据流的数值转换算法及硬件实现

利用RNS(余数数制系统)可以执行并行的数据处理以及实现快速无进位算法,在VLSI(超大规模集成电路)设计中表现出低功耗、占用面积小和时延少等优良特性.根据中国剩余定理,基于(2n-1)2n(2n+1)模组,利用Verilog语言设计了RNS到位数据流的数值转换接口电路.以使传统的多位数(Bit)的复杂运算转化为多个并行的较少位数的简单运算,从而降低单次运算的复杂度、时延和功耗.该转换电路面向"Σ-Δ"编码的数据流,不同于传统的二进制数据转换,可以方便地与基于DSD(Direct Stream Digital)的Delta-Sigma系统进行无缝连接.     

HGHD:一种基于超图的高维空间数据聚类算法

传统聚类算法无法有效地处理现实世界中存在许多高维空间数据。为此，提出一种基于超图横式的高维空间数据聚类算法HGHD,通过数据集中的数据及其间关系建立超图横型，并应用超图划分进行聚类，从而把一个求解高维空间数据聚类问题转换为一个超图分割寻优问题。该方法采用自底向上的分层思想，相对于传统方法最大的优势是不需要降维。直接用超图模式描述原始数据之间的关系，能产生高质量的聚类结果。     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.     

Hybrid genetic-paired-permutation algorithm for improved VLSI placement

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N²).     

A connectivity based clustering algorithm with application to VLSI circuit partitioning

Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks-ISPD98 benchmark suite. The experimental results show that by applying the proposed clustering algorithm, the previously reported best partitioning solutions from state-of-the-art partitioners are further improved.     

An area-efficient very large scale integration architecture for modified Euclidean algorithm with dynamic storage technique

A Modified Euclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties, an area-efficient very large scale integration (VLSI) architecture with dynamic storage technique is proposed to perform the ME algorithm. The dynamic storage technique is used to avoid data exchange and save hardware resources. The proposed architecture with dynamic storage technique can reduce 50% computation hardware area and about 30% memory hardware area. VLSI implementation results of different RS codes show that the proposed architecture is significantly area-efficient, especially for RS codes with long code lengths.     

Enhanced multi-level filter algorithm and its VLSI architecture

This paper presents an enhanced multi-level filter algorithm and its Very Large Scale Integration (VLSI) architecture for infrared image processing. The modified multi-level filter algorithm resolves the splitting targets problem using Gaussian pyramid processing. Owning three filtering paths, the proposed VLSI architecture of the filter can simultaneously enhance small targets with different sizes in infrared images. Some design techniques in implementing hardwired multiplication, subsample and asynchronous FIFO have been presented. This VLSI architecture has been implemented using Semiconductor Manufacturing International Corporation (SMIC) 0.35?µm 4-layer CMOS technology. The simulation results show that it not only effectively suppresses background, eliminates noise and enhances small targets in an infrared image comparing with other small target detective methods, but also meets infrared image real-time processing requirements (5?M?～?10?M pixels/s). The implemented filter chip consists of 60,284 gates and 8?K Static Random Access Memory (SRAM), operates at 50?MHz.     

三维互连电感电阻的快速提取

VLSI电路的特征尺寸已降至深亚微米量级,频率已达2GHz.为保证高性能电路设计的正确性,需快速而精确地计算互连寄生电感电阻.本文提出了一种适合三维层次互连结构的描述格式,提出一种考虑趋肤效应的电流细丝自动划分方法,实现了改进的非均匀立方体划分多极加速计算.数值结果表明,在可比精度下,它比当前十分先进的多极加速提取软件FastHenry^[1]快数倍以至数十倍.     

二维DCT算法及其精简的VLSI设计

采用了快速算法,并通过矩阵的变化,得到了一维离散余弦变换(Discrete Cosine Transform,DCT)的一种快速实现,并由此提出一种精简的超大规模集成电路(Very-large-scale integration,VLSI)设计架构.使用了一维DCT的复用技术,带符号数的乘法器设计等技术,实现了二维DCT算法的精简的VLSI设计.实验结果表明,所设计的二维DCT设计有效,并能够获得非常精简的电路设计.