用于200V电平位移电路的薄层SOI高压LDMOS

文章基于1.5μm厚顶层硅SOI材料,设计了用于200 V电平位移电路的高压LDMOS,包括薄栅氧nLDMOS和厚栅氧pLDMOS。薄栅氧nLDMOS和厚栅氧pLDMOS都采用多阶场板以提高器件耐压,厚栅氧pLDMOS采用场注技术形成源端补充注入,避免了器件发生背栅穿通。文中分析了漂移区长度、注入剂量和场板对器件耐压的影响。实验表明,薄栅氧nLDMOS和厚栅氧pLDMOS耐压分别达到344 V和340 V。采用文中设计的高压器件,成功研制出200 V高压电平位移电路。     

应用于负电源的电平位移电路及器件设计

本文设计了一种应用于负电源的电平位移电路。实现从0～8V低压逻辑输入到8～-100V高压驱动输出的转换。分析了该电路的结构和工作原理。基于此电路结构设计了满足应用要求的高压薄膜SOI LDMOS器件。分析了器件的工作状态以及耐压机理,并利用工艺器件联合仿真对器件的电学特性进行了优化设计。     

基于耦合式电平位移结构的高压集成电路

设计并实现一种耦合式C型(coupled)高压电平位移结构,避免常用S型结构中LDMOS漏极高压互连线(HVI)跨过器件源侧及高压结终端时的两处高场区,以直接耦合式实现了高压电平位移和高低压隔离,且减小了芯片面积.借助Pwell,Nepi,P-sub所形成的JFET效应增加C型结构中隔离电阻;引入金属场板MFP,防止LD-MOS的栅、漏与高压结终端多晶场板短接.利用作者开发的高压SPSM CD工艺,成功研制出基于C型电平位移结构的1000V三相功率MOS栅驱动集成电路.结果表明,C型电平位移结构的最高耐压为1040V,较常用S型结构提高了62.5%,所研制的1000V电路可满足AC220V,AC380V高压领域的需要.     

基于耦合式电平位移结构的高压集成电路

设计并实现一种耦合式C型(coupled)高压电平位移结构,避免常用S型结构中LDMOS漏极高压互连线(HVI)跨过器件源侧及高压结终端时的两处高场区,以直接耦合式实现了高压电平位移和高低压隔离,且减小了芯片面积.借助Pwell,Nepi,P-sub所形成的JFET效应增加C型结构中隔离电阻;引入金属场板MFP,防止LD-MOS的栅、漏与高压结终端多晶场板短接.利用作者开发的高压SPSM CD工艺,成功研制出基于C型电平位移结构的1000V三相功率MOS栅驱动集成电路.结果表明,C型电平位移结构的最高耐压为1040V,较常用S型结构提高了62.5%,所研制的1000V电路可满足AC220V,AC380V高压领域的需要.     

一种低功耗高稳态电平位移电路

提出了一种新型低功耗、高稳态电平位移电路。该电路能将5 V输入电压转换为10 V输出电压,在电路的初态和电平转换过程中均保持高稳态。采用瞬态增强结构,能加速电平信号之间的转换,有效地减小了传输延迟,提高了电路稳定性。瞬态增强结构在稳定状态时不发挥作用,减小了静态功耗,获得了低功耗。基于标准0.35 μm BCD工艺和多5 V LDMOS耐压器件,对该电平位移电路在5 MHz频率下进行验证。结果表明,动态功耗仅为24.8 μA,上升沿响应速度仅为12.7 ns,下降沿响应速度仅为22.8 ns。该电路具有可靠性高、功耗低的优点。     

基于中低压器件实现的高压负电平位移电路

提出了一种新型高压负电平位移电路.该电路只采用中低压PM()S来实现高压电平位移,与传统的高压负电平位移电路相比,降低了工艺及器件难度.分析了该新型电平位移电路的电路结构与工作原理.采用1μm CMOS工艺,通过HSPICE进行电路仿真验证,证明提出的高压负电平位移电路正确可行.     

一种同步降压型DC-DC转换器驱动电路设计

设计了一种适用于同步整流降压型DC-DC转换器的驱动电路,包含电平移位、死区时间控制及过零检测等模块。分析了电路整体及各个模块的结构和工作原理,并基于0.35 μm BCD工艺模型库,通过Cadence Spectre进行仿真验证。仿真结果表明,本电路可以有效地控制死区时间,抑制反向电流,提高转换器的效率。     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

1.6 MHz降压型DC-DC转换器中的斜率补偿设计

PWM电流模控制方式在DC-DC转换器设计电路中得到了广泛应用,也带来了斜率补偿问题.讨论了降压型DC-DC转换器中斜率补偿技术的原理,分析了传统的线性补偿技术并详细介绍了一种改进的分段线性补偿电路,给出了在1.6 MHz降压转换器中的实际应用电路.电路基于CSMC 0.5 μm CMOS工艺设计,通过Cadence Spectre仿真验证,该斜坡补偿电路有效解决了子谐波振荡以及过补偿问题.     

一种应用于双通道卫星导航接收机的高效率低噪声电源解决方案

本文提出了一种应用于双通道卫星导航接收机的高效率低噪声电源解决方案,主要包括降压型DC-DC转换器和低压差稳压器。为了获得更好的噪声抑制和抗干扰性能,应用脉冲宽度调制(PWM)作为DC-DC转换器的控制方式。提出了一种改进的低功耗PWM控制电路,通过周期性的关断跨导放大器,将转换器的平均静态功耗降低了一半,并且具有较高的工作频率。针对双通道接收机的特点,对输出级功率管的尺寸进行了优化,使效率最优。另外,提出了一种基于限流原理的新型软启动电路,无须使用片外大电容或数模转换器,降低了设计复杂度。电路使用180nm CMOS工艺流片,测试结果显示,DC-DC转换器在2MHz的工作频率下拥有最高93.1%的转换效率,整个双通道接收机在3.3V电源供电下仅消耗电流20.2mA。     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.     

基于LM5117P的降压型直流开关稳压电源设计

降压型直流开关稳压电源是一种单向DC-DC变换器,实现稳定直流降压功能.本系统采用同步降压控制器LM5117P作为电路控制核心,以同步Buck电路作为降压主电路,通过闭环回路反馈设计以及芯片本身的精准采样,将输入电压16V降为5V恒压输出.     

A DC-DC converter for short-channel CMOS technologies

An integrated DC-DC converter with two passive external components was designed and fabricated in an advanced, short-channel (L_eff <0.2 μm, V_dd<2 V) CMOS technology. This design was undertaken to examine the feasibility of implementing an inductive buck converter with passive components small enough to fit entirely within a packaged chip. High switching frequencies (>10 MHz) were used to minimize the size of external components, and novel circuits were used to reduce the stress on the short channel devices. Measured efficiencies for a 3.3 V to 1.65 V converter were approximately 75% for output currents from 15 to 40 mA     

Low-voltage-swing monolithic dc-dc conversion

A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter.     

Design of anti-jamming current-sensing circuit for current-mode buck regulator

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented.Based on the widely-used traditional current-sensing structure,anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit.Also the transient response is faster through the introduction of current offset.The circuit iS concise,simple to implement and suits for SoC applications with single power supply.A dual-output current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5μm CMOS process for validation.In the 2.5-5.5 V input range,the two channels work steadily in the load current range of 0-600 mA.And the measured maximum efficiency is up to 96%.