基于VMM的外部存储器接口验证

随着SoC规模和复杂度的增加,功能验证变得越来越复杂,传统的验证方法很难对其进行全面的验证.基于SystemVerilog语言和VMM(Verification Methodology Manual)的高级验证方法学,采用覆盖率驱动、带有约束的随机化和断言等验证方法设计验证平台,对外部存储器接口进行了功能验证.验证结果表明,此验证平台能够实时监测覆盖率,控制验证进程,优化验证事务,代码和功能覆盖率可达100%.该方法简化验证复杂度,提高验证平台的可重用性,较好地满足芯片验证需要.     

利用VMM建立基于事务的层次化验证平台

VMM是一种基于SystemVerilog语言的验证方法学,它通过引入断言、抽象化、自动化与重用这四种机制提高了项目验证的生产率。本文通过一个实例介绍怎样利用VMM建立基于事务的可重用的层次化验证平台。     

基于SynoTPys VMM方法的FPGA验证技术

针对可编程器件在数字系统设计领域日益显现的重要性,分析了基于现场可编程门阵列(FPGA)的硬件设计的质量保证方法,指出必须对FPGA设计进行充分的验证以提高相应产品的可靠性.从验证方法和方法学角度阐述了验证平台的发展趋势,比较了当前主流的验证方法学,基于Synopsys VMM方法提出并实现了一种层次化的通用验证技术,运用该技术搭建的验证平台已在工程实践中得到应用,验证结果表明,在保证平台通用性的同时提高了验证效率.     

基于Synopsys VMM方法的FPGA验证技术

针对可编程器件在数字系统设计领域日益显现的重要性,分析了基于现场可编程门阵列(FPGA)的硬件设计的质量保证方法,指出必须对FPGA设计进行充分的验证以提高相应产品的可靠性.从验证方法和方法学角度阐述了验证平台的发展趋势,比较了当前主流的验证方法学,基于Synopsys VMM方法提出并实现了一种层次化的通用验证技术,运用该技术搭建的验证平台已在工程实践中得到应用,验证结果表明,在保证平台通用性的同时提高了验证效率.     

功能覆盖率驱动的TAU/MVBC模块验证*

本文基于验证方法学(VMM),使用硬件验证语言搭建分层可复用的TAU/MVBC验证环境,利用功能覆盖率结果对随机激励生成器进行导向,同时使用断言覆盖未达到的边角情况,在合理的时间内达到了预定的覆盖率要求。结果表明,覆盖率导向的带约束随机激励生成方法通过提高对覆盖率贡献较大的小概率事件出现的次数,有效地提高了验证效率。     

基于SystemVerilog可重用测试平台的实现

对于中小型设计,传统的验证效率低、可重用性差,而基于方法学的高级验证测试平台搭建较繁琐,验证流程不太灵活。以ARINC429收发器IP核为验证对象,采用System Verilog语言,通过层次化设计,改善工程组织架构,运用虚接口与回调等关键技术,实现了一种可重用测试平台。将不同的测试案例在测试平台上运行,结合断言与覆盖率驱动等验证技术完成了对ARINC429收发器IP核的功能验证,代码覆盖率和功能覆盖率均达到100%。实践表明,该测试平台具有良好的可重用性、易操作性,验证效率较高。     

基于SystemVerilog的向量存储器验证方法

随着半导体工艺的发展,片上存储器的设计容量和复杂度日益增长,传统的功能验证方法面临着验证完备性、可重用性、效率和可靠性等方面挑战.针对自主设计的某16路SIMD结构的大容量向量存储器(vector memory,VM)覆盖率驱动的验证方法进行研究,基于SystemVerilog验证方法学,采用层次化建模方法搭建了高效的VM验证平台,在较高抽象层次上实现了带约束的随机激励,结合SVA断言技术对向量存储器向量读访存流水线的同步与提交状态实时监控,保证了关键时序逻辑功能验证的完备性、正确性,有效提高了验证效率.最终模块级验证结果表明,定向激励和随机激励相结合能较快达到理想的代码覆盖率.     

基于功能覆盖率的MAC的UVM验证

论文基于UVM验证方法学,以及覆盖率驱动的芯片验证指导思想,搭建并分析了高度可重用的以太网控制器IP的验证平台.为了提高验证效率,论文对MAC的工作流程进行了研究,对其功能点进行了划分,针对性地编写了测试用例.在测试用例的驱动下,对MAC的数据收发功能进行了全流程的仿真验证.在大规模随机测试用例和定向测试用例的共同作用下,加快了验证所需要的时间,节省了仿真所需的计算机资源,达到了功能覆盖率100％的目标.     

龙腾Stream流处理器验证

芯片设计复杂度的提高迫切地需要先进的方法学以应对巨大的验证工作量。通过开发基于System Verilog的覆盖率驱动的自动化验证平台,对龙腾Stream流处理器的指令集进行了功能验证。实验结果表明,该验证平台提高了验证效率和功能覆盖率,具有良好的重用性和可移植性。搭建FPGA原型验证系统对流处理器的功能和系统性能进行了评测,并提出了优化流处理器加速性能的方法。     

基于Avalon-MM的I2C总线控制器设计及VMM验证

分析了Avalon-MM总线的架构以及I2C总线的传输方式,提出了一种可行的I2C总线控制设计方案,并说明了详细的实现过程；设计的基于Avalon-MM总线的I2C总线控制器可复用IP核,可以不加修改地应用在基于Altera公司产品的SOPC系统中；使用VMM验证方法学构建了多层次可复用的验证平台,对设计进行了全面的验证；整个验证平台使用systemverilog语言实现,仿真工具使用VCS-MX200606；最后仿真结果显示,设计被完全地验证并达到100%覆盖率。     

基于多项式符号代数方法的高层次数据通路的等价验证

基于BDD或布尔SAT的等价验证方法虽然能够成功验证低层次门级电路,但却难以满足高层次设计验证要求.由此,以多项式符号代数为理论基础,提出了一个高层次数据通路的等价验证算法.深入研究了使用多项式表达式描述复杂数据通路行为的方法,得到了高层次数据通路的多项式集合表示的一般形式.从多项式集合公共零点的角度定义了高层次数据通路的功能等价,给出了一个基于Gr(o)bner基计算的有效代数求解算法.针对不同基准数据通路的实验结果表明了该算法的有效性.     

Verifying the FM9801 microarchitecture

Hardware verification accounts for a considerable portion of the costs in the microprocessor design process. Traditionally designers have verified microprocessor designs using simulation techniques that help find most design faults. However, simulation never guarantees the correct operation of the final product. Some design faults are very difficult to detect by simulation; they may slip through the verification process into manufactured chips, raising costs. We believe that verification costs can be reduced by the judicious application of formal methods, which should lower the overall costs of design     

Ontology-based requirement verification for complex systems

Verification is a necessary part of Model-based systems engineering (MBSE) which is becoming a mainstream methodology for the design of complex systems. Verification in the early design stage has aroused widespread attention for its efficiency and cost-saving. Although there are numbers of researches on verification, some deficiencies still exist, such as the integration of design and verification needs to improve, the design problems are hard to trace and the behavior verification in the early design stage is often omitted. In this study, a novel ontology-based requirement verification method for complex systems is proposed to solve the above-mentioned problems. First, a requirement formalization method is proposed to avoid the ambiguousness of natural language, to make requirements easier to verify, and to make design problems easier to trace. Second, some transformation rules are defined to realize the automatic design ontology and rule generation. Based on these two steps, automated verification can be done through reasoning with ontology models and rules. This verification method is fully integrated with design tools and no additional expertise is needed for designers. To validate its feasibility and advantages, an example of a smart traffic light system is provided.     

Design validation: comparing theoretical and empirical results ofdesign error modeling

To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results     

Design and development paradigm for industrial formal verificationCAD tools

CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve. This article discusses a few fundamental design decisions behind the successful deployment of a second-generation formal custom-memory equivalence-checking tool, Versys2, in the PowerPC design flows. The Versys2 symbolic simulator was developed at Motorola for verifying equivalence between register-transfer-level (RTL) designs and custom transistor circuit schematics     

Constraint-based functional design verification for conceptual design

In the early stages of mechanical product design, designers not only need to determine the physical structure of the design, but also need to verify that the design functions properly with the allowable values or ranges of values of the relevant design attributes. Existing work on design verification is either aimed at specific design problems, which are generally carried out at the downstream design stages, or aimed at deriving design behavior using a behavioral simulation approach. Functional design verification has largely been neglected by the research society. To tackle this problem, we propose a generic constraint-based approach that is based on a comprehensive functional design model. A number of strategies are proposed for the approach, including strategies for design variables reduction, variable dependency graph development, constraint propagation, and dynamic verification of a design over an assigned set of attributes (variables). The approach is implemented as part of a functional modeling design environment. A simple design verification case is presented to illustrate our approach.     

实时系统的形式化验证

实时系统的设计对系统设计人员而言是一个巨大挑战。在缺乏严格的验证环境时 ,要避免设计错误是很困难的。本文将一种带时戳的时序逻辑及用于描述具体实时系统的时间变迁系统编码到 HOL定理证明器中 ,并实现了一个基本的规则策略库 ,从而实现了一个简单的交互式辅助验证环境L RP。实例 Fisher算法的互斥性在 IRP中得到了验证。     

VDVAS：一个集成的虚拟设计与虚拟装配系统

随着虚拟现实技术的逐渐成熟，研究者们已将其引入到工程领域，为实现虚拟设计与虚拟装配过程的集成，避免现有的虚拟装配系统中，虚拟环境与CAD系统间所必需进行的复杂的、无谓的数据传输，描述了一个基于多通道的、集成的虚拟设计与虚拟装配系统VDVAS。在该系统中，设计得可以通过直接三维操作和语音命令直观方便地建立机械零件及其装配模型，并通过交互拆装来得到零件的装配顺序和装配路径等信息，VDVAS的一个重要特征在于，可通过集成虚拟设计与虚拟装配过程，使设计者能在一个集成的虚拟环境中修改零件几何（假如在装配过程中发现零件存在设计缺陷的话）。     

The KlaperSuite framework for model-driven reliability analysis of component-based systems

Automatic prediction tools play a key role in enabling the application of non-functional requirements analysis, to simplify the selection and the assembly of components for component-based software systems, and in reducing the need for strong mathematical skills for software designers. By exploiting the paradigm of Model-Driven Engineering (MDE), it is possible to automatically transform design models into analytical models, thus enabling formal property verification. MDE is the core paradigm of the KlaperSuite framework presented in this paper, which exploits the KLAPER pivot language to fill the gap between design and analysis of component-based systems for reliability properties. KlaperSuite is a family of tools empowering designers with the ability to capture and analyze quality of service views of their systems, by building a one-click bridge towards a number of established verification instruments. In this article, we concentrate on the reliability-prediction capabilities of KlaperSuite and we evaluate them with respect to several case studies from literature and industry.     

Conceptual prototyping of scalable embedded DSP systems

This systematic process uses model-based architectural synthesis and verification to ensure that early stages of the design are efficient, economical, and meet user requirements. Using a scalable, plug-and-play, model year methodology, designers can conceptually prototype complex, embedded digital systems in weeks instead of months