使用单位增益缓冲器构成的抗寄生SC跨导

用单位增益缓冲器构成的开关电容滤波器(SCF),若能消除寄生电容引起的阻性寄生,则可用于高频设计,总寄生灵敏度会因此大大降低。本文在此基础上提出一种新的抗寄生开关电容(SC)跨导元件电路差分跨导元件,并用它构成了适用于高频的SC浮地电感和积分器。最后用它实现了一个三阶椭圆函数低通滤波器,并经计算机模拟和实验验证,证明了该方案的正确性。     

对寄生电容不灵敏的开关电容有源FDNR滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭园函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭园低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

对寄生电容不灵敏的开关电容有源滤波器的设计

采用单位缓冲器设计对寄生电容不灵敏的开关电容(SC)频率相关负电阻(FDNR)元件，利用该元件对椭圆函数式LC低通滤波器进行SC模拟。为了获得电容最佳值，提出了一种简单的最优化方法；并采用寄生电阻预畸变与SC负电阻相结合的办法，设计的SC滤波器对寄生电容不灵敏，且电路简单。在电子工作平台(EWB)上进行五阶椭圆低通SC-FDNR滤波器仿真，测量数据最大相对误差为0．948％，仿真结果表明该方法实用可行，效果明显。     

A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

Low-voltage and high-frequency Gm-opamp-C filter with automatic self frequency tuning

A 1.0 V, 10 MHz Gm-opamp-C filter is described. For low voltage and high frequency operation, the number of internal nodes is minimized to avoid the generation of parasitic poles and the number of stacked transistors between VDD and GND is limited to two. The frequency response of the filter is automatically tuned by a simple self tuning circuit. The measured dynamic range of the filter is 47 dB while dissipating 5 mA.     

SC filter circuit with decimation of sampling frequency

Realisation of a switched-capacitor filter circuit with decimation of the input sampling frequency is proposed. The circuit, which is compensated for the influence of parasitic capacitances, is useful as an input stage of an SC filter. It can also be used for the realisation of an integrator, based on Simpson's rule.     

基于新型缺陷地的谐波抑制微带滤波器设计

由于分布参数传输线频率响应的周期性,通常微带线带通滤波器在偏离主通带中心频率成分上会产生寄生通带,输出谐波.在研究经典哑铃DGS的基础上,利用新型DGS和SISS结构的单极点带阻和慢波特性,设计出五阶微带低通滤波器,并将之应用于三阶耦合线带通滤波器,改善其寄生通带.经过仿真验证,成功地抑制了三阶耦合线带通滤波器的谐波输...     

Design techniques for high-frequency CMOS switched-capacitorfilters using non-op-amp-based unity-gain amplifiers

A fully differential non-op-amp-based unity-gain amplifier (UGA) is proposed, whose 3-dB frequency can be as high as 250 MHz in 3.5-μm p-well CMOS technology. The purpose is to develop a new design concept for high-frequency switched-capacitor (SC) filters which uses balanced non-op-amp type UGAs with tunable gain to replace conventional op-amp-based unity-gain buffers (UGBs). The proposed UGA has a normal gain of unit, but it has a greater bandwidth, better setting behavior, smaller chip area, and less transistors than op-amp-based UGB. The new UGA also has a fully differential balanced configuration. The balanced configuration and proper predistortion by CAD tools can reduce the error due to linear parasitic capacitances. Experimental results prove the capability of the proposed structures in the realization of high-frequency SC filters over the megahertz range     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.     

基于交指谐振结构的微带低通滤波器改进设计

提出一种微带低通滤波器改进设计方法.滤波器本身采用经典方法设计,通过在输入输出端口上添加交指型谐振器构成带阻滤波器,可将滤波器的适用带宽拓展50%以上.采用的交指型谐振器由8根容性交指和1根感性的高阻抗线并联而成,通过调整交指长度,可以方便地调节谐振器的谐振频率.设计并制作了两种改进结构,数值模拟和测量结果表明:通过引入交指结构,可以有效抑制微带低通滤波器的寄生通带,并且可以通过级联多个交指谐振器进一步扩展滤波器的适用频带.该设计方法还可用于带通等其他类型微带滤波器的寄生通带抑制.     

高阻带抑制LTCC 滤波器的设计与实现*

提出了一种基于LTCC技术的新型高阻带抑制带通滤波器的实现方法.采用在并联谐振器的圆柱形电感之间引入感性耦合,在高阻带产生一个传输零点,并且能实现非常好的阻带衰减性能.本文对传统的梳状线带通滤波器结构进行改进,利用过孔的寄生电感效应,将过孔用作谐振杆,明显减小了器件的尺寸.并且通过利用空间耦合的寄生效应,实现滤波器的阻带高抑制传输零点,以满足了对特殊频点高抑制的要求.运用该方法设计了中心频率1.65 GHz,通带200MHz,带外2GHz处衰减大于60dBc的五级带通滤波器.实物测试结果和全波电磁仿真结果吻合较好.     

基于缺陷地抑制高阶谐波的带通滤波器设计

采用微带线设计的平行耦合滤波器(MCL-BPF)在通带以外往往产生谐波,出现寄生频段。利用缺陷地结构(Defected Ground Structure,DGS)的单极点带阻特性和慢波效应可以改善寄生通带,抑制谐波输出。对2.4GHz的传统微带平行耦合滤波器和改进型带通滤波器进行了仿真设计与加工测试。实测结果与仿真数据良好吻合,所提出基于斜哑铃型DGS的带通滤波器(S-DGS-BPF)可抑制至四阶谐波,抑制度达到-22dB以下,阻带为3-10GHz,中心频率处回波损耗为-26.93dB。并且改进型滤波器的尺寸缩小了约10%。     

Novel parasitic insensitive SC large pole selectivity (Q) bandpass fitter with less capacitor spread and low pole ‘Q’ sensitivity

A new parasitic insensitive switched capacitor (SC) bandpass filter scheme is presented. The selectivity of the bandpass filter can be made very high without large capacitor spread, hence the proposed circuit consumes less chip area in monolithic integration and passive sensitivities of the circuit are found to be low.     

New realization of inductances for switched-capacitor filters using voltage inverter switches

This paper describes a new design method of inductance simulation for switched-capacitor (SC) filters based on the VIS-SC concept. The resulting circuits have not only the excellent sensitivity behavior of VIS-SC filters, but also the low sensitivity to the main parasitics occuring in the MOS integrated circuit, i.e., the parasitic capacitances between the bottom plates of the implemented capacitors and substrate. As examples, a sixth-order band-pass and a sixth-order band-stop elliptic filter transformed from a third-order low-pass are given. Experimental results agree very well with theory. A brief analysis is given of certain parasitic effects in band-stop filters at the Nyquist frequency.     

Pi型电感耦合LTCC滤波器的寄生感性耦合研究

对二阶Pi型电感耦合LTCC滤波器中各个元件的电容及电感寄生效应进行了分析,提出了一种新的寄生电感耦合分析方法,并根据分析结果设计了一个二阶Pi型电感耦合和一个二阶Pi型电容耦合LTCC带通滤波器,其中,电感耦合滤波器的设计指标为:中心频率2.45GHz,相对带宽32.65%,带内插入损耗2dB,回波损耗18 dB;电...     

寄生电感对低压增强型GaN HEMT开关行为的影响

寄生电感是影响功率管开关特性的重要因素之一,开关频率越高,寄生电感对低压增强型氮化镓高电子迁移率晶体管(GaN HEMT)的开关行为影响越深,使其无法发挥高速开关的性能优势。通过建立数学模型,理论分析了考虑各部分寄生电感后增强型GaN HEMT的开关过程,并推导了各阶段的持续时间和影响因素,然后通过建立双脉冲测试平台,对各部分寄生电感对开关特性的具体影响进行了实验验证。实验结果表明,寄生电感会使开关过程中的电流、电压出现振荡,影响开关速度和可靠性,并且各部分寄生电感对增强型GaN HEMT的开关过程影响程度不同,在实际PCB布局受到物理限制时,需要根据设计目标优化布局,合理分配各部分寄生电感以获得最优的开关性能。     

Resonant clocking using distributed parasitic capacitance

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.     

OTA-C Filters with Finite Zeros

In this paper we present a novel technique for OTA-C filter realizations with finite zeros based on doubly loaded passive ladder networks. Only grounded capacitors are needed; all floating capacitors are replaced with active simulations eliminating bottom-plate parasitic capacitors and non-observable poles. Bandpass, highpass and bandstop filters are easily obtained from a lowpass OTA-C prototype applying standard frequency transformations that preserve the active simulation of floating capacitors, i.e. the finite zeros realization. Also, we address the high frequency stability problem of highpass and bandstop OTA-C filters simulating doubly loaded passive ladder networks. These filters usually have floating nodes where the OTA excess-phase acting over the nodal parasitic capacitance can introduce unstable poles at high frequencies. The stability problem is fairly the same for highpass and bandstop OTA-C filters based on approximations with and without finite zeros; only the most complex case (filters with finite zeros) will be addressed here.     

分数阶微积分对频域除噪技术的改进

频域除噪是信号降噪技术中的重要内容。由于噪声多为高频,频域除噪技术一般利用低通滤波器滤除含噪信号中的高频部分,以达到除噪的目的。然而图像信号的轮廓以及某些细节部分也为高频,会被低通滤波器当作噪声滤除,降低除噪效果。利用分数阶微积分,对滤波器算法进行细微变换和调整,使其能够更加精确地区分噪声与高频信号,从而在滤除噪声的同时更多地保留高频信号部分。文中通过大量的仿真,证明了该方法较传统的滤波除噪技术具有很大的进步性。