基于指令流混合比与功能单元匹配的软错误脆弱性控制方法

发射队列是处理器流水线的关键结构,,降低发射队列对软错误的敏感性已成为微处理器可靠性设计不可忽视的问题。本文提出一种在处理器流水线前端实施的软错误脆弱性控制方法,该方法在不改变功能单元的情况下,根据指令流混合比与功能单元配置的匹配情况,调节发射队列中的指令类型比例,降低指令在发射队列中的等待时间,从而降低发射队列的体系结构脆弱因子,缓解软错误敏感性。实验结果表明该方法平均减低发射队列的架构易感因子2.8%左右,IPC/AVF提高约4.9%。     

基于SimpleSim-ARM模拟器的软错误易感性分析与评估

随着集成电路特征尺寸的逐步缩小,随之而来快速增长的软错误率严重限制了现代微处理器的应用,因此对微处理器可靠性进行评估十分重要。在微处理器体系结构级进行软错误易感性评估能反映出微处理器部件的可靠性,提出基于SimpleSim-ARM模拟器对微处理器体系结构级进行软错误易感性评估的方法,可用于对ARM体系结构微处理器进行软错误易感性评估。根据提出方法对StrongARM SA-11xx进行软错误易感性分析,实验结果表明,在基准配置情况下,存储部件中寄存器文件的平均AVF值为57.76%;非存储部件发射队列（IQ）、保留站与重定序缓冲（RUU）与功能单元（FUs）的平均AVF值分别为38.53%、32.02%和12.39%。在不同配置下,IQ和RUU部件容量越大,对应部件AVF评估值越小;FUs数量越多,该部件AVF评估值越小。     

微处理器体系结构级软错误易感性评估

随着集成电路特征尺寸的缩小和集成度的增加,微处理器的软错误问题越来越严重。为了提高微处理器的可靠性,设计者需要在体系结构设计时精确估算各个部件的软错误率,从而对各部件进行相应的容错设计。本文针对微处理器中的软错误问题,研究了体系结构级软错误易感性估算模型,基于该模型对超标量微处理器主要部件的软错误易感性进行定量分析,并讨论了可靠性与性能的折衷设计。实验结果对微处理器软错误的预防和保护具有一定指导意义,也为微处理器主要部件的容错设计提供了参考。     

一种快速有效的L2 Cache可靠性预测方法

随着集成电路工艺的不断进步,微处理器的软错误问题日益突出.体系结构弱点因子AVF(architectural vulnerability factor)作为可靠性评估指标之一,常用于软错误的评估.AVF在程序执行过程中呈现明显的动态变化特性,使得基于AVF预测的动态容错管理技术成为当前软错误研究领域的热门课题.即根据AVF的变化来动态选择是否对微处理器部件进行容错设计,从而在满足软错误可靠性要求的前提下尽量降低容错技术的开销.因此,基于L2 Cache AVF的动态特性研究,提出使用贝叶斯累加树模型BART(Bayesian additive regression trees)对L2 Cache AVF进行准确预测,并使用块搜索( bump hunting)技术来提取由少数几个性能参数组成的、对具有高L2 Cache AVF的执行阶段进行判定的规则,从而实现了对L2 Cache AVF的快速有效预测.     

基于软错误的动态程序可靠性分析和评估

基于软件实现的软错误容错方法不需要硬件开销,被认为是一种高效的软错误容错方法,而动态的实现这种方法能覆盖更多种类型的程序,因而能覆盖更多的软错误,分析硬件软错误对程序执行时代码和数据的逻辑影响,并建立了硬件软错误条件下程序运行可靠性评估模型.本文的工作为基于软件动态软错误容错算法的提出提供了理论基础,也为程序可靠性的评估提供了一种方法.我们依据体系结构层硬件对指令执行的影响将硬件构件进行分类,并分析了不同的硬件构件对程序代码和数据的逻辑影响.基于软错误对程序代码和数据的影响模型,建立了软错误条件下程序运行可靠性评估模型.最后,在实验中,对软错误条件下程序影响模型和程序运行可靠性评估模型进行了验证,实验结果证明了本文的分析和评估结果.     

面向分布式流体系结构的多副本积极容错技术

随着互联网环境下计算系统规模的不断扩大,分布式流体系结构的可靠性问题面临着严峻的挑战。以多模冗余容错技术为基础,针对软错误提出了一种面向分布式流体系结构的多副本积极容错技术TREFT,利用三个程序副本进行高效的检错与纠错。在分布式流体系结构原型系统上的实验结果表明,该技术能有效提高系统的可靠性,具有较低的容错成本,平均增加10.77%的容错开销。     

面向软错误的寄存器活跃区间分析

继性能和功耗问题之后,软错误导致的计算可信性已成为一个日益严峻的课题.由于寄存器访问频繁却未能被良好保护,发生在其中的软错误成为影响系统可靠性的关键因素之一.基于程序汇编代码,提出一种针对寄存器软错误的程序可靠性静态分析方法.首先通过数据流分析技术提取出可能影响程序执行的寄存器活跃区间,然后基于构成活跃区间的基本块集合计算其有效体系结构易感位数,在此基础上可定量计算寄存器软错误影响下的程序可靠性.基于MiBench基准程序的实验表明,该方法的分析结果与AVF分析法保持一致,同时还指出了寄存器相关活跃区间的关键程度,这为实现针对寄存器软错误的高效容错方法提供了依据.     

一种面向多核处理器I/O系统软错误容错方法

集成电路制造工艺的飞速发展,使得集成电路的特征尺寸不断减少和集成度不断提高,造成集成电路对工作环境的影响越来越敏感,发生软错误的几率不断增加,对可靠性造成重要影响。随着微处理器进入了多核时代,丰富的片上资源给软错误加固带来了很好的机遇。本文针对多核处理器中I/O系统软错误,提出了一种基于多核处理器的软件Scrub方法对软错误进行加固。测试结果表明,我们提出的软错误容错方法可以大大提高I/O系统的可靠性。     

寄存器软错误对程序可靠性影响的静态分析

继性能和功耗问题之后,软错误导致的计算可信性已成为一个日益严峻的课题。其中,由于寄存器访问频繁却未能被良好保护,发生在其中的软错误成为影响程序可靠性的关键因素之一。基于程序汇编代码,提出一种针对寄存器软错误的程序可靠性静态分析方法。首先通过数据流分析技术提取所有可能影响程序执行的寄存器活跃区间,然后基于活跃区间的路径表达式分析其执行时间和出现频率,最后在此基础上计算在寄存器软错误影响下的程序可靠性。实验表明,该方法的分析结果与AVF分析法保持一致,同时其结果还指出相关的寄存器活跃区间的执行时间和出现频率,这为实现针对寄存器软错误的高效容错方法提供了依据。     

微处理器可靠性AVF评估方法研究综述

架构脆弱因子（AVF）表示处理器结构中导致程序输出可见错误的故障概率, 可量化故障屏蔽效应, 使得定量分析架构的故障率不受底层变量的影响, 是微处理器设计环节中一个重要的可靠性度量指标。介绍AVF的基本概念、计算方法, 对相关研究进展进行梳理, 指出现有AVF研究方法的局限性, 并探讨了未来的研究方向。     

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

With continuous technology scaling,on-chip structures are becoming more and more susceptible to soft errors.Architectural vulnerability factor (AVF) has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors.Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e.,issue queue,reorder buffer).Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes (ECC).However,protecting caches closer to the processor (i.e.,L1 data cache (L1D)) using ECC could result in high overhead.Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection.Therefore,designing AVF-aware ECC is attractive for designers to balance among performance,power and reliability for cache,especially at early design stage.In this paper,we improve the methodology of cache AVF computation and develop a new AVF estimation framework,soft error reliability analysis based on SimpleScalar.Then we characterize dynamic vulnerability behavior of L1D and detect the correlations between L1D AVF and various performance metrics.We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF.Then,we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics,thus enabling a simplified and fast estimation of L1D AVF.Based on the simplified and fast estimation of L1D AVF,intervals of high L1D AVF can be identified online,enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC.Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program,AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.     

DNA计算机中队列数据结构的设计及实现

提出了DNA计算机中队列数据结构的设计方法,该方法利用两种不同的限制性内切酶完成队列的入队和出队操作,并给出了队列的DNA编码和仿真实例.首先给出了DNA计算机中队列存储结构的形式描述;然后详细给出了DNA计算机中队列初始化、入队和出队等操作的生物实现方法;最后给出了一个具体算法的实例,仿真了DNA计算机上该算法的运行机制.仿真结果表明文中提出的队列的设计方法在DNA计算机上切实可行.这种方法可推广到DNA计算机上其他类型的数据结构,帮助DNA计算机合理、有效地组织需要处理的信息,从而使DNA计算机走向实际应用.     

基于拓扑序列归约的Web服务组合QoS度量算法

考虑有向无环图 (DAG)描述的组合服务模型,提出了一种新的组合服务QoS度量方法--基于拓扑序列归约的Web服务QoS度量方法（QCMTSR）。其借鉴迭代归约度量方法中的基本结构及QoS计算公式,定义了DAG图中的两类基本结构,串归约结构和并归约结构,并给出了两种基本结构的QoS属性计算公式;通过逐步归约DAG图拓扑序列中的每个节点,直至最后一个节点的QoS属性值就是组合服务的各QoS属性的度量结果。从理论上证明了QCMTSR算法适用于所有DAG描述的组合服务,并实验证明QCMTSR算法对可靠性和可用性能够更准确的度量。     

Revisiting priority queues for image analysis

Many algorithms in image analysis require a priority queue, a data structure that holds pointers to pixels in the image, and which allows efficiently finding the pixel in the queue with the highest priority. However, very few articles describing such image analysis algorithms specify which implementation of the priority queue was used. Many assessments of priority queues can be found in the literature, but mostly in the context of numerical simulation rather than image analysis. Furthermore, due to the ever-changing characteristics of computing hardware, performance evaluated empirically 10 years ago is no longer relevant. In this paper I revisit priority queues as used in image analysis routines, evaluate their performance in a very general setting, and come to a very different conclusion than other authors: implicit heaps are the most efficient priority queues. At the same time, I propose a simple modification of the hierarchical queue (or bucket queue) that is more efficient than the implicit heap for extremely large queues.     

Optimal Measurement-based Pricing for an M/M/1 Queue

In this paper, we consider a system modelled as an M/M/1 queue. Jobs corresponding to different classes are sent to the queue and are characterized by a delay cost per unit of time and a demand function. Our goal is to design an optimal pricing scheme for the queue, where the total charge depends on both the mean delay at the queue and arrival rate of each customer. We also assume that those two values have to be (statistically) measured, introducing errors on the total charge that might avert jobs from using the system, and then decrease demand. This model can be applied in telecommunication networks, where pricing can be used to control congestion, and the network can be characterized by a single bottleneck queue; the throughput of each class would be determined through passive measurements while the delay would be determined through active measurements.     

Design and implementation of a queue compiler

Queue processors are a viable alternative for high performance embedded computing and parallel processing. We present the design and implementation of a compiler for a queue-based processor. Instructions of a queue processor implicitly reference their operands making the programs free of false dependencies. Compiling for a queue machine differs from traditional compilation methods for register machines. The queue compiler is responsible for scheduling the program in level-order manner to expose natural parallelism and calculating instructions relative offset values to access their operands. This paper describes the phases and data structures used in the queue compiler to compile C programs into assembly code for the QueueCore, an embedded queue processor. Experimental results demonstrate that our compiler produces good code in terms of parallelism and code size when compared to code produced by a traditional compiler for a RISC processor.     

异构计算环境下基于优先队列划分的调度算法

人工智能的飞速发展对高性能计算提出了更高的要求,异构计算环境下任务调度问题一直是高性能计算中的关键问题.本文提出一种基于优先队列划分的调度算法(PQDSA),该算法根据DAG(有向无循环图)任务集的入口节点数量确定优先队列数,通过任务的通信开销和计算开销划分任务队列,进而将关键节点任务分配给合适的队列,以产生效果较佳的任务调度队列,从而提高任务间的并行性,降低任务集的完工时间.与此同时,进一步基于插入策略将任务调度到处理器上,使任务调度更加高效地执行.PQDSA算法可以减少任务间的时间消耗,提高处理器的调度效率.通过与两个经典算法的性能对比,实验结果表明本文提出的PQDSA算法在任务完工时间和调度效率方面都要明显优于对比的算法.