一种Ling选择进位加法器

设计一种Ling选择进位加法器,组间采用Ling进位代替传统的进位,利用内部连线与节点扇出平衡的并行前缀逻辑产生进位机制,并对通常的进位选择模块进行调整,以使其适合Ling进位。该加法器兼具了Ling加法器的快速性,又避免了逻辑产生的复杂性。实验结果表明,与超前进位加法器相比,该加法器的速度提高12％左右。     

5加数并行加法器及其进位接口

传统加法器在处理多操作数累加时,必须进行多次循环相加操作。针对该问题设计5操作数并行加法器及其高速进位接口。电路采用多操作数并行本位相加和底层进位级联传递的方式,在一定程度上实现多操作数间的并行操作,减少相加次数。模拟结果验证了该加法器的设计合理性,证明其能缩短累加时间、提高运算效率。     

VLIW数字信号处理器64位可重构加法器的设计

描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构，可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。仿真结果表明，在典型工作条件下，采用0.18μm工艺库标准单元，其关键路径的延时为0.83ns，面积为0.149mm2，功耗仅为0.315mW。     

原理图输入方法设计32位超前进位加法器

本文介绍了用原理图输入方法设计一款图象处理ASIC芯片中乘加单元的核心运算部件——32位超前进位加法器，出于速度(时延)和面积折衷优化考虑，它以四位超前进位加法器和四位超前进位产生器为基本设计单元级联而成，因此该电路具有速度和面积的折衷优势。选择原理图输入方法，是考虑到本电路复杂度不高，而原理图输入可控性好，效率高，可靠性强且直观，可以熟悉较底层的结构。文章先给出电路的设计实现，并且是先设计四位超前进位加法器，再提出32位超前进位加法器的设计思想和设计原理，然后再通过测试文件的逻辑验证正确。本设计的所有内容，都将在SUN工作站上Cadence工具Schematic Composer中完成。     

数字信号处理器中高性能可重构加法器设计

设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18μm工艺库标准单元,其延时降低46%,功耗降低5%。     

基于组间进位预测的快速进位加法器

为加快密码系统中大数加法的运算速度,提出并实现一种基于组间进位预测的快速进位加法器。将参与加法运算的大数进行分 组,每个分组采用改进的超前进位技术以减少组内进位延时,组间通过进位预测完成不同进位状态下的加法运算,通过每个组产生的进位状态判断最终结果。性能分析表明,该进位加法器实现1 024位大数加法运算的速度较快。     

PRNS加法中先行进位算法的研究

ＰＲＮＳ算法是运算器内部的并行机制。在ＰＲＮＳ数母全加器的研制中，找到了一种新的先行进位算法，提出了ＰＲＮＳ先行进行产生器的逻辑结构。     

快速进位的高速加法器

本文介绍了采用饱和晶体管快速进位电路的试验性高速二进制并行加法器。加法器由进位链、进位与求和控制电路、进位放大器以及求和电路构成。加法器电路的性能优良并且其逻辑结构简单,只需要较少组件。本文略述其操作原理,而详细地叙述加法器电路的研制,也涉及到进位传送的实验结果。当进位链上的开关晶体三极管在进位信号加入以前就已经达到饱和时,36位的进位传送时间需要80毫微秒。     

一种专用进位链优化设计

提出了一种适合FPGA高效运算的专用进位链结构.基于应用范围方面的考虑.我们先对典型的行波进位做了一定的改进.目的是增强逻辑模块的功能实现能力和提高运算速度.提出进位链设计的策略.设计一种基于高效加法器像选择进位、超前进位的进位新结构.结果表明这种优化设计提高了芯片的运算速度,同时比现有的结构要快2倍左右.     

改进部分积压缩结构的快速乘法器

针对16位乘法器运算速度慢、硬件逻辑资源消耗大的问题,采用华莱士树压缩结构,通过对二阶布思算法、4-2压缩器和保留进位加法器的优化组合使用及对符号数采用合理的添、补、删策略,实现16位符号数快速乘法器的优化设计。该乘法器采用SMIC 0.18 μm工艺标准数字单元库,使用Synopsys Design Compiler综合实现,在1.8 V, 25℃条件下,芯片最大路径延时为3.16 ns,内核面积为 50 452.75 μm2,功耗为5.17 mW。     

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.     

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

Lane of parallel through carry in ternary optical adder

At the present 50 to 100 microseconds are necessary for a liquid crystal to change its state from opacity to clarity; 1.14×10-5 microseconds are however proved to be enough for light to pass through a clarity liquid crystal device. Rooted from this great difference in time, an optical adder was constructed with parallel through carry lanes (PTCL) composed of liquid crystals. Because all carries in PTCL process in parallel, the carry delay in the ternary optical computer's adder is avoided. Eliminating the carry delay in adder of ternary optical computer by physical means, the PTCL is also applicable for other types of optical adders. Moreover a light diagram of the adder and one PTCL structure are provided.     

Performance enhancement of efficient process based on Carry-Skip Adder for IoT applications

IoT provides a platform for every device to be connected by means of a stable internet connection. The interoperability of the devices helps to communicate and exchange data between one another and increases the power consumption of devices. When creating a new IoT system or rebuilding the existing ones, the low power circuit design is considered as an essential factor. In the low power circuit design, the most challenging aspect to overcome is to reduce the leakage power, because the battery-operated devices are fast in draining energy when left long in the standby mode. Reducing the delay of a ripple carry adder can be only accomplished with Carry-Skip Adder (CSA) with minimal effort when compared to other techniques like a carry-look ahead adder. The carry skip adder belongs to the family of bypass adders, and its main aim is to improve the worst-case delay of the IoT device based on its area and power consumption. The CSA used in the proposed method for the IoT processor helps to increase the performance of the system relative to average power dissipation, leakage power, power delay product, and propagation delay.     

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.     

Comparative study of FFA architectures using different multiplier and adder topologies

Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.

     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.