一种新颖的峰值电流模式DC-DC Buck片上快速软启动电路

A fully integrated soft-start circuit for DC-DC buck converters is presented.The proposed high speed soft-start circuit is made of two sections:an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor.A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current.The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13μm CMOS process.Experimental results show that the proposed high speed soft-start circuit has achieved less than 50μs start-up time.The inductor current and the output voltage increase smoothly over the whole load range.     

一种具有动态零点补偿的电流模DC-DC降压型转换器

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm~2.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.     

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

A double-stage start-up structure to limit the inrush current used in current mode charge pump

A double-stage start-up structure to limit the inrush current used in current-mode charge pump with wide input range, fixed output and multimode operation is presented in this paper. As a widely utilized power source implement, a Li-battery is always used as the power supply for chips. Due to the internal resistance, a potential drop will be generated at the input terminal of the chip with an input current. A false shut down with a low supply voltage will happen if the input current is too large, leading to the degradation of the Li-battery''s service life. To solve this problem, the inrush current is limited by introducing a new start-up state. All of the circuits have been implemented with the NUVOTON 0.6 μm CMOS process. The measurement results show that the inrush current can be limited below 1 A within all input supply ranges, and the power efficiency is higher than the conventional structure.     

一种用于高压降压型转换器的高精度强驱动能力驱动电路

This paper presents a novel driving circuit for the high-side switch of high voltage buck regulators.A 40 V P-channel lateral double-diffused metal–oxide–semiconductor device whose drain–source and drain–gate can resist high voltage, but whose source–gate must be less than 5 V, is used as the high-side switch. The proposed driving circuit provides a stable and accurate 5 V driving voltage for protecting the high-side switch from breakdown and achieving low on-resistance and simple loop stability design. Furthermore, the driving circuit with excellent driving capability decreases the switching loss and dead time is also developed to reduce the shoot-through current loss. Therefore, power efficiency is greatly improved. An asynchronous buck regulator with the proposed technique has been successfully fabricated by a 0.35 m CDMOS technology. From the results, compared with the accuracy of16.38% of the driving voltage in conventional design, a high accuracy of 1.38% is achieved in this work. Moreover,power efficiency is up to 95% at 12 V input and 5 V output.     

A Novel Ultra Low Power High Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth

A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/℃ is achieved over -25 to 125 ℃ temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm².     

Design of anti-jamming current-sensing circuit for current-mode buck regulator

A novel anti-jamming integrated CMOS current-sensing circuit for current-mode buck regulators is presented.Based on the widely-used traditional current-sensing structure,anti-jamming performance is improved significantly by adding on-chip capacitors and one-shot circuit.Also the transient response is faster through the introduction of current offset.The circuit iS concise,simple to implement and suits for SoC applications with single power supply.A dual-output current-mode DC-DC buck converter with proposed structure has been fabricated with a 0.5μm CMOS process for validation.In the 2.5-5.5 V input range,the two channels work steadily in the load current range of 0-600 mA.And the measured maximum efficiency is up to 96%.     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

一款电流型控制的DC／DC降压转换器

本文提出一种新型电感电流检测电路,该检测电路不需要一个放大器作为电压镜像,从而使用的器件更少,功耗更低。该电感电流检测电路应用于DC／DC降压转换器,采用CSM 0．18μm CMOS工艺进行设计和仿真,仿真结果显示该电感电流检测电路的精度可达到96％,输出电压的纹波仅为1mV。     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

A current-mode buck DC-DC controller with adaptive on-time control

A current-mode buck DC-DC controller based on adaptive on-time (AOT) control is presented. The on-time is obtained by the techniques of input feedforward and output feedback, and the adaptive control is achieved by a sample-hold and time-ahead circuit. The AOT current-mode control scheme not only obtains excellent transient response speed, but also achieves the independence of loop stability on output capacitor ESR. In addition, the AOT current-mode control does not have subharmonic oscillation phenomenon seen in fixed frequency peak current-mode control, so there is no need of the slope compensation circuit. The auto-skip pulse frequency modulation (PFM) mode improves the conversion efficiency of light load effectively. The controller has been fabricated with UMC 0.6-μm BCD process successfully and the detailed experimental results are shown.     

降压变换器片内集成软启动电路设计

针对电流模降压变换器的集成化趋势,提出了一种可片内集成的软启动电路. 该结构利用芯片振荡器产生的窄脉冲信号,控制微电流对片内电容间歇充电得到斜坡电压,并巧妙地利用复合比较器以较小的功耗实现了对峰值电流的限制,避免了浪涌电流,完成了软启动功能. 提出的软启动电路结构简单、易于实现,减少了芯片引脚数目,降低了PCB面积,并在一款基于0.5μm CMOS工艺设计的降压型DC-DC中进行了投片验证. 测试结果表明,3.6V输入1.8V输出600mA负载电流在使能140μs后芯片成功实现了软启动.     

Adaptive Sliding-Mode Position Control for Piezo-Actuated Stage

The effect and design criteria of the input filter for buck converters with peak current-mode (PCM) control are researched using a novel system block diagram. With this diagram, a novel current loop transfer function is proposed to derive the design criteria that apply to designing the input filter. However, the input filter that is added to reduce electromagnetic interference will significantly change the dynamic property of the PCM-controlled buck converter. Therefore, the induced effect due to the input filter is examined. Finally, experimental results prove the accuracy of this deduction in both the circuit simulation and the circuit experiment.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

Multi-loop control for quasi-resonant converters

A multiloop control scheme for quasi-resonant converters (QRCs) is described. Like current-mode control for pulse width modulation (PWM) converters, this control offers excellent transient response and replaces the voltage-controlled oscillator (VCO) with a simple comparator. In this method, referred to as current-sense frequency modulation (CSFM), a signal proportional to the output-inductor current is compared with an error voltage signal to modulate the switching frequency. The control can be applied to either zero-voltage-switched (ZVS) or zero-current-switched (ZCS) QRCs. Computer simulation is method applied to a ZCS buck QRC. A circuit implementation is presented that allows multiloop control to be used on circuits switching up to 10 MHz. This circuit requires few components and produces clean control waveforms. Experimental results are presented for zero-current flyback and zero-voltage buck QRCs, operating at up to 7 MHz. Good small-signal characteristics have been obtained     

电流模降压DC-DC内部补偿研究

利用片内补偿实现了一款单片电流模降压型DC-DC变换器。设计的分段线性斜坡补偿电路大大缓解了传统线性方法的过补偿问题,提高了系统响应速度。集成的RC频率补偿结构克服了稳定性对输出负载以及陶瓷输出电容ESR的依赖,简化了设计,节省了PCB面积。芯片基于标准0.5μm CMOS工艺实现,内部补偿实现了良好的环路稳定性,负载调整率以及线性调整率均小于0.4%,400 mA负载阶跃对应输出电压的响应时间小于8μs。同步整流技术使得效率高达94%。