基于向量传播的单粒子瞬态模拟方法研究

提出了一种基于向量传播的单粒子瞬态(SET)模拟方法。基于4值参数的模型来表征SET脉冲的形状,建立脉冲参数传播的数据库。使用查找表及经验公式来计算SET脉冲形状参数在逻辑门节点之间的传播。为了模拟SET脉冲在传播过程中的重汇聚,定义了4种重汇聚模式,并给出对应的等效脉冲计算方法。提出的基于向量传播的分析算法能够对SET脉冲的产生、传播及捕获过程进行精确分析。ISCAS''89电路的实验结果表明,该方法与Hspice仿真方法的平均误差为1.827%,计算速度提升了1 700倍。在不损失精度的前提下,该方法可对VLSI电路在通用或特定测试向量下的可靠性进行快速自动分析。     

考虑多时钟周期瞬态脉冲叠加的锁存窗屏蔽模型

集成电路工艺水平的提升,使得由单粒子瞬态脉冲造成的芯片失效越发不容忽视．为了准确计算单粒子瞬态脉冲对锁存器造成的失效率,提出一种考虑多时钟周期瞬态脉冲叠加的锁存窗屏蔽模型．使用提出的考虑扇出重汇聚的敏化路径逼近搜索算法查找门节点到达锁存器的敏化路径,并记录路径延迟;在扇出重汇聚路径上,使用提出的脉冲叠加计算方法对脉冲进行叠加;对传播到达锁存器的脉冲使用提出的锁存窗屏蔽模型进行失效率的计算．文中的锁存窗屏蔽模型可以准确计算扇出重汇聚导致的脉冲叠加,并对多时钟周期情形具有很好的适用性．针对ISCAS’85基准电路的软错误率评估结果表明,与不考虑多时钟周期瞬态脉冲叠加的方法相比,文中方法使用不到2倍的时间开销,平均提高7．5％的软错误率评估准确度．     

NBTI效应导致SET脉冲在产生与传播过程中的展宽

本文研究了负偏置温度不稳定性(NBTI)对单粒子瞬态(SET)脉冲产生与传播过程的影响.研究结果表明:NBTI能够导致SET脉冲在产生与传播的过程中随时间而不断展宽.本文还基于工艺计算机辅助设计模拟软件(TCAD)进行器件模拟,提出了一种在130nm体硅工艺下,计算SET脉冲宽度的解析模型,并结合NBTI阈值电压退化的...     

SET传播过程中的脉冲展宽效应

利用SPICE电路模拟研究了SET在传播过程中的脉冲展宽效应.结果表明,负载的不均衡、电路上/下拉网络驱动能力的不对称以及浮体效应是造成脉冲展宽/压缩的主要原因. 本文从基本的上升/下降延迟计算出发,对脉冲展宽/压缩的机理进行了深入的分析,认为在负载均衡的条件下,SOI反相器链中的脉冲展宽效应主要归因于浮体效应和“局部”浮体效应.     

SET传播过程中的脉冲展宽效应

利用SPICE电路模拟研究了SET在传播过程中的脉冲展宽效应.结果表明,负载的不均衡、电路上/下拉网络驱动能力的不对称以及浮体效应是造成脉冲展宽/压缩的主要原因.本文从基本的上升/下降延迟计算出发,对脉冲展宽/压缩的机理进行了深入的分析,认为在负载均衡的条件下,SOI反相器链中的脉冲展宽效应主要归因于浮体效应和"局部"浮体效应.     

组合逻辑电路中的软错误（Soft Error）生成模型的分析

在深亚微米集成电路设计领域,电路可靠性问题日益严重。这个问题的一个重要方面是组合逻辑电路的软错误。现有的关于软错误率的分析和模型表明电压脉冲宽度对电气掩蔽（Electrical Masking）以及锁存窗掩蔽（Latch Window Masking）两种效应都有很大的影响。电压脉冲的宽度通过影响这两种效应进而决定了电路的软错误率。但是这些分析和模型在这个问题上不够深入。在这篇文章中,我们首次提出一个脉冲生成的解析模型。这个模型表明,越过一个拐点后,电路中由射线粒子注入的电荷量同电压脉冲宽度之间存在指数关系。这个模型的平均误差约为2.6%。这个模型还揭示了逻辑门延时与软错误率之间的折中关系。这个关系是最近的一篇有关组合逻辑电路软错误率降低方法的论文的基础[19]。     

单粒子瞬态效应硬件注入模型实现和仿真

基于量化组合逻辑门延迟思想和扫描测试的方法,提出了一种适用于FPGA硬件模拟单粒子瞬态效应的门级注入模型.该模型考虑了电气掩蔽效应对脉冲传输的影响,通过该模型可以对组合电路任意逻辑门进行错误注入.基于该模型对ISCAS’85基准电路进行单粒子瞬态的研究,实验结果表明该脉冲产生方法高效,注入速度达到105 faults/s.     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

基于保护门的纳米CMOS电路抗单粒子瞬态加固技术研究

随着器件特征尺寸的缩减,单粒子瞬态效应(SET)成为空间辐射环境中先进集成电路可靠性的主要威胁之一。基于保护门,提出了一种抗SET的加固单元。该加固单元不仅可以过滤组合逻辑电路传播的SET脉冲,而且因逻辑门的电气遮掩效应和电气隔离,可对SET脉冲产生衰减作用,进而减弱到达时序电路的SET脉冲。在45 nm工艺节点下,开展了电路的随机SET故障注入仿真分析。结果表明,与其他加固单元相比,所提出的加固单元的功耗时延积(PDP)尽管平均增加了17.42%,但容忍SET的最大脉冲宽度平均提高了113.65%,且时延平均降低了38.24%。     

复杂数字电路中的单粒子效应建模综述

单粒子效应产生的软错误是影响航天电子系统可靠性的主要因素之一。对其进行建模是研究单粒子效应机理和电路加固技术的有效方法。介绍了深亚微米及以下工艺中影响模型准确性的几种效应机制,包括脉冲展宽机制、电荷共享机制和重汇聚机制等。重点分析了单粒子瞬态、单粒子翻转的产生模型和单粒子瞬态的传播模型。阐述了基于重离子和脉冲激光的模型验证方法。最后,分析了单粒子效应随特征尺寸的变化趋势,并提出了未来单粒子效应建模技术的发展方向。     

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.     

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS’85 and ITC’99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures.     

基于概率转移矩阵的时序电路可靠度估计方法

传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PIM计算模型得到电路的PIM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.     

纳米CMOS电路的单粒子瞬态影响因素研究

进入纳米尺度后,单粒子瞬态(SET)成为高能粒子入射VLSI产生的重要效应,准确、可靠的SET模拟对评估VLSI的可靠性有着重要的影响。以反相器为例,针对脉冲峰值和半高全宽两个指标,研究了电路模拟中影响SET的因素,主要有电流脉冲幅值、脉冲宽度、负载电容、环境温度及器件尺寸。通过对45和65 nm两种技术节点下的电路的仿真,研究了这些因素对SET的影响,并探讨了可能的原因。结果显示,这些因素对SET的影响趋势和程度有很大的差异,且器件尺寸越小,这些因素对SET的影响越显著。通过设置合适的参数,可以实现电路的抗辐射加固。     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

结合版图结构信息的基本门电路故障概率估计

在门级电路可靠性估计方法中,基本门的故障概率P一般采用经验值或人为设定.本文结合基本门的版图结构信息,综合考虑了设计尺寸及缺陷特性等因素,分析了不同缺陷模型下的粒径分布数据,给出了缺陷模型粒径概率密度分布函数的参数c的计算算法,并推导出了P的计算模型.理论分析与在ISCAS85及74系列电路上的实验结果表明,缺陷的分段线性插值模型能较准确地描述电路可靠性模型的低层真实缺陷.对ISCAS85基准电路采用本文方法所得到的电路可靠度与采用美国军用标准MIL-HDBK-217方法所得到的计算结果进行了比较,验证了本文所建P模型的合理性.     

The impact of Miller and coupling effects on single event transient in logical circuits

With feature size scaling down, Miller feedback effects of gate-to-drain capacitance for transistors and coupling effects between interconnects will dramatically affect single event transient (SET) generation and propagation in combinational logic circuits. Two ways of ICs are arranged: linear and “S” types. For pulse width and delay time, SET propagations in two layouts of digital circuits are compared under considering the coupling effects between interconnects. An analytical model is used to describe the impact of Miller and coupling effects on SET propagation. A criterion for SET occurrence in digital circuits with effects of coupling and Miller feedback is presented. The influence of temperature and technology node on SET generation and propagation is analyzed. The results indicate that (1) the existence of these effects will improve the critical charge for SET generation and also reduce the estimated SER, and (2) the way of “S” type is more immune to SET than the scheme of linear.     

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching (PIPBQ) effect become more noticeable. In order to effectively evaluate the soft error rate for combinational logic circuits, a soft error rate analysis approach considering the PIPBQ effect is proposed. As different original pulse propagating through logic gate cells, pulse broadening and quenching are measured by HSPICE. After that, electrical effect look-up tables (EELUTs) for logic gate cells are created to evaluate the PIPBQ effect. Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm. Further, by propagating pulses on these paths to simulate fault injection, the PIPBQ effect on these paths can be quantified by EELUTs. As a result, the soft error rate of circuits can be effectively computed by the proposed technique. Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.