一种基于全差分积分器的时钟稳定电路设计

设计了一种用于超高速A/D转换器的时钟稳定电路。利用全差分连续时间积分器将差分时钟信号的占空比量化为电压信号,再通过跨导放大器产生控制电流来调整输出时钟的共模电平,达到调整输出时钟占空比的目的。电路采用0.18 μm标准CMOS工艺进行设计,工作电压为1.8 V,在2 GHz的最高时钟频率下,将占空比为20%~80%的输入时钟信号调整为(50±1)%,输出时钟抖动小于132 fs,具有抑制时钟抖动的能力。     

一种用于高速高精度A/D转换器的时钟稳定电路

设计了一种完全满足高速高精度流水线A/D转换器的时钟稳定电路.通过在延迟环路中加入启动电路,使环路能在小于300 ns内快速锁定占空比,锁定精度为50%±1%.拥有20%～80%的占空比输入,且能很好地抑制外部时钟抖动,时钟抖动小于100 fs.电路采用0.35 μm工艺制作,芯片面积为0.5 mm×0.3 mm,在3.3 V电源电压下,功耗小于78 mW.     

应用于高性能延迟锁相环的占空比修正电路设计

设计了一款应用于高性能延迟锁相环的占空比修正电路。该电路主要由差分放大电路、占空比调整电路、缓冲器电路和占空比检测电路组成,采用TSMC 40 nm CMOS工艺和1.1 V的电源电压。仿真的结果表明,时钟频率2 GHz～8 GHz,占空比20%～80%的输入时钟信号,经过占空比修正电路调节后,输出时钟信号占空比变为50%±0.2%,可应用于高性能延迟锁相环中。     

一种新型超高速高精度时钟占空比校准电路

设计了一种超高速高精度时钟占空比校准电路。采用一种新的脉冲宽度校准单元,通过控制电压调整时钟上升、下降时间来实现占空比调整。同时,设计了一种时钟放大模块,降低了占空比校准单元对输入时钟幅度的要求,提高了占空比校准精度。分析了各电路模块的作用以及对整体性能的影响。采用SMIC 65 nm CMOS工艺,在1.8 V电源电压下对各模块以及整体电路进行仿真验证。仿真结果表明,该时钟占空比校准电路能对输入频率为1～4 GHz、占空比为20%～80%的时钟进行精确校准,校准后的占空比为(50±1)%,系统稳定时间为200个输入时钟周期,功耗为10 mW。     

一种新型差分脉宽控制环路的设计

设计了一种新型时钟稳定电路～差分脉宽控制电路.用参考电路产生参考电压,避免因采用环形振荡器等方法产生大的时钟抖动.同时,在控制电路部分用交叉耦合正反馈来调节时钟占空比.该电路采用0.18 μm工艺,电源电压为1.9 V,输入时钟占空比调节范围为25%～75%,时钟频率为2 GHz,时钟抖动小于200 fs.     

面向电荷泵的占空比可调四相时钟发生电路北大核心

针对传统四相时钟发生电路产生的时钟波形信号易发生交叠、驱动电荷泵易发生漏电等问题，提出了一种占空比可调四相时钟发生电路。电路在每两相可能出现交叠的时钟信号之间都增加了延时单元模块，通过控制延时时间对输出时钟信号的占空比进行调节，避免了时钟相位的交叠。对延时单元进行了改进，在外接偏置电压条件下，实现了延时可控。基于55 nm CMOS工艺的仿真结果表明，在10～50 MHz时钟输入频率范围内，该四相时钟发生电路可以稳定输出四相不交叠时钟信号，并能在1.2 V电压下驱动十级电荷泵高效泵入11.2 V。流片测试结果表明，该四相时钟发生电路能够产生不相交叠的四相时钟波形，时钟输出相位满足电荷泵驱动需求。     

一种应用于EEPROM的片上电荷泵电路设计

设计了一种应用于EEPROM的片内电荷泵电路系统。该电路基于Dickson电荷泵结构,通过使用稳定的参考电压驱动压控振荡电路,从而产生了占空比小于50%的精确时钟,提高了电荷泵升压速度;通过使用调压电路,限制并稳定了输出电压。HSPICE仿真结果显示:在5 V电源电压下,时钟频率高达2.085 MHz。电荷泵仅需要56.256μs就可以输出15.962 V的高压。电荷泵的电压上升时间快,性能优越。     

一种高速高精度时钟占空比稳定电路

设计了一种高速高精度的时钟占空比稳定电路。采用全差分连续时间积分器将时钟占空比量化为电压信号,积分器对占空比偏差的累积效应可使电路达到很高的调整精度。采用跨导运算放大器将电压信号转换为电流信号,并加载到输入时钟缓冲器上,改变其输出时钟的直流电平,从而调整输出时钟的占空比,避免了调整输出时钟上升/下降沿带来的较大抖动。采用TSMC 0.18 μm CMOS工艺进行设计,电源电压为2 V。当输入差分时钟频率为1.6 GHz时,可以将占空比范围为20%~80%的输入时钟信号的占空比均调节至(50±0.5)%,且输出时钟抖动小于159.398 fs,适用于超高速的信号处理系统。     

纯数字时钟50%占空比调节电路设计

利用数控延迟线原理和脉冲电路特性设计实现了一种纯数字方式的高性能时钟50%占空比调节电路FD-DCC (Full-Digital Duty-Cycle Corrector ),不包括任何反馈环路,可产生无偏时钟.经0.13 μm工艺版图实现后的SPICE模拟表明,该电路在200～400 MHz频率范围内工作稳定,对占空比在10%～90%范围内的畸变时钟能进行高精度的调节,输出时钟占空比为50%±2%,且输出时钟和原始时钟间相位偏差较小.     

DC/DC变换电路的仿真研究

该文阐述了直流斩波电路(Buck电路和Cuk电路)的电路结构和工作原理,并利用Multisim进行了电路的仿真。首先运Multisim画出Buck电路和Cuk电路的仿真原理图,并设置了采集输出电压的电压表和电流表和示波器,然后分别分析电力MOSFET在导通和关闭时的电路工作状态,电流流经路径,以此推导Buck电路和Cuk电路的输入电压与输出电压关系,要实现降压,Buck电路的占空比α调节范围0～1之间,Cuk电路的占空比α调节范围0～50%。然后使用画出的原理图进行仿真电路的工作波形,使用24V的直流输入电压,得到12V的直流输出电压,Buck电路的占空比设置为50%,通过仿真结果分析得出Buck电路的输出电压是11,768V,Cuk电路占空比33.3%,输出电压为-12.2V,与分析的输出电压极性与输出电压极性相反,数值是正确的,且要求的误差小于5%。通过调节Buck电路和Cuk电路的占空比可以将输入直流电压斩波变换为输出电压不等的电压值。     

A single-path pulsewidth control loop with a built-in delay-locked loop

A 1-1.27-GHz single-path pulse width control loop with a built-in delay-locked loop is presented. Based on the proposed circuit, not only can the 50% duty cycle of the output clock be assured but the phase alignment between the reference and output clocks can also be achieved. Moreover, the requirement of the reference clock with 50% duty cycle can be eliminated. By the single-to-complementary circuit and the switched charge pump, the duty cycle error can be reduced. Moreover, the duty cycle of the output clock can be adjusted for applications such as time-interleaved analog-to-digital converters, switched-capacitor circuits, and dc-dc converters. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS process. The power consumption is 150 mW and the die area of the core circuit is 0.47/spl times/0.3 mm/sup 2/. The duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.     

A differential pulsewidth control loop for high-speed VLSI systems

For those adopting double data rate technology systems, the precise system timing plays a crucial role since both rising and falling edges of the system clock signal are used to sample the input data. Due to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. For a multistage clock buffer, a pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of its output signal. This paper is aimed at introducing a new proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis. By taking advantage of a differential topology, the dc offset in generating the control voltage can be removed thereby improving the duty cycle control accuracy. Moreover, the proposed DPWCL employs a low-pass filter to generate the reference voltage so that the DPWCL does not necessitate a 50% duty cycle reference clock.     

一种4路正交时钟校准电路的设计

采用TSMC 40 nm CMOS工艺,设计了一种正交时钟校准电路,它包含2个脉冲宽度调整环路和1个内嵌的延迟锁相环。与其他校准电路相比,本文校准电路无需50%占空比的参考时钟或者单端转差分(STC)电路,就能获得4路占空比为50%的时钟,还能调整时钟的相对相位以输出4路正交时钟。当工作频率为3.125 GHz时,该校准电路能将占空比为10%~90%的输入时钟自动调整至占空比为50%±0.2%的时钟,相位调整范围为58°~122°,电路功耗为2.2 mW,可应用于RapidIO物理层接收机电路中。     

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-/spl mu/m CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

CMOS digital duty cycle correction circuit for multi-phase clock

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50/spl plusmn/0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 /spl mu/m CMOS technology is used in this work.     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.