Low-voltage low-power CMOS RF low noise amplifier

In this paper, a 1 V, 2 GHz CMOS low-noise amplifier (LNA) was developed intended for use in the front-end receiver. The circuit is simulated in standard $0.25\mathrm{\mu }\mathrm{m}$ CMOS MOSIS. The LNA gain is 25.675 dB, noise figure (NF) is 4 dB, reverse isolation $(S_{12})$ is $-134.3\mathrm{dB}$, input return loss $(S_{11})$ is $-14.6\mathrm{dB}$, output return loss $(S_{22})$ is $-13.34\mathrm{dB}$, and the power consumption is 5.13 mA from a single 1 V power supply. One of the features of the proposed design is using a three-component cascode limitation, one of it is a transistor, to reduce the supply voltage.     

Study on the physical properties of europium doped indium oxide thin films

Structural, morphological, optical and electrical properties of europium doped In₂O₃ thin films grown by spray pyrolysis technique are studied in this work. The atomic percentages of europium dopant in In₂O₃-based solution were y = ${\left(\frac{{[\mathit{Eu}}^{3+}]}{{[\mathit{In}}^{3+}]}\right)}_{\mathit{sol}}$=0; 0.1; 0.3 and 0.5 at%. All films crystallize into the body centered cubic structure. The preferred orientation peak along the (222) plane was changed to (400) after doping. It is further revealed a best crystallinity for y =0.3 at% followed by a noticeable increase of the grain size. Some structural and microstructural parameters are determined using Rietveld refinement of XRD patterns. The optical transmission of doped films was above 68% in the visible range. The optical band gap (E_g) is in the range of [3.43–3.51] eV. Optical constant such as refractive index (n), packing density (p), porosity, oscillator energy (E₀) an_d dispersive energy (E_d) were also studied in this report using envelope method based on transmission-reflection spectra. Electrical properties show a lowest resistivity (ρ) for a doping concentration equals to 0.3 at% reaching 0.031 Ω cm. At this doping ratio, an enhancement of free carrier concentration is also remarked. A heat treatment under nitrogen atmosphere is then applied on optimized In₂O₃:Eu (0.3 at%). A significant decrease of the resistivity is noted at 250 °C during 2 h reaching 0.004 Ω cm. These results lead to conclude that annealed In₂O₃:Eu(0.3 at%) can be a good candidate to be used in many optoelectronic devices and especially as optical window or transparent electrode in solar cells.     

Effect of hyperthermal annealing on LPCVD silicon nitride

The objective of this paper is to understand the effects of 1100 °C annealing on film thickness, refractive index and especially residual stress of low-pressure chemical vapor deposition (LPCVD) silicon nitride films. The annealing effect on Young's modulus of silicon nitride films is also discussed. For these purposes, a number of 1100 °C furnace annealing processes in N₂ atmosphere were carried out. With the increase of annealing time, film thickness decreases exponentially and correspondingly the refractive index increases. Both film thickness and refractive index reach a stable value after several times annealing. Due to the film densification and viscous flow, residual stress of $\mathrm{Si}–{\mathrm{Si}}_3{\mathrm{N}}_4$ system increases in the first 10 min annealing treatment and then decreases in the following annealing processes. Based on the Maxwell viscoelastic model, an improved model which considers film densification and viscous flow simultaneously is built to explain the effect of annealing process on residual stress.     

A miniaturized broadband bow-tie antenna with improved cross-polarization performance

In this paper, a modified broadband bow-tie antenna with low cross-polarization level and miniaturization is presented. The cross-polarization in both E- and H-planes are suppressed by defecting the antenna flares using rectangular slots. The proposed modified antenna demonstrated a cross-polarization improvement over $\pm 120°$ around the boresight from 2 to 5 GHz. In addition, an overall 23.5% of miniaturization compared to conventional bow-tie antenna is achieved. A tapered feed transition between microstrip-to-parallel stripline is designed to match 50 ohm SMA connector to the antenna flares. A prototype of the modified antenna is fabricated on RO4003 substrate ($\epsilon$_r = 3.38, tan $\delta$ = 0.0027, h = 0.813 mm), and its performance is experimentally studied. The antenna’s characteristics including return loss, gain and radiation pattern are measured, along with the time domain characteristics, and showed reasonable agreement with the simulated results.     

Theoretical and numerical investigations of carriers transport in N-semi-insulating-N and P-semi-insulating-P diodes – A new approach

A new and simple theoretical model is developed for ambipolar transport in compensated N-semi-insulating (SI)-N or P-SI-P diodes and is validated with exact J–V_a characteristics obtained through numerical modelisation. The electrical parameters used correspond to SI GaAs layers, but these results are valid for other compounds such as SI InP and InGaP. A relation between the bulk non-equilibrium excess carrier concentrations, valid for low and intermediate applied voltage, is first established. For a deep donor (N_t) compensating a residual shallow acceptor (N_A): $(n-n_{\text{e}})\approx \frac{{\tau }_{\text{nt}}}{{\tau }_{\text{pt}}}\left(\frac{N_{\text{t}}-N_{\text{A}}}{N_{\text{A}}}\right)(p-p_{\text{e}})$, where n_e and p_e are the thermal equilibrium free carrier densities in the SI layer, τ_nt, τ_pt and n_1t, p_1t are the familiar Shockley–Read–Hall (SRH) parameters of the deep trap. This relation represents an extension of the well known quasi space charge neutrality condition: (n ? n_e) ≈ (p ? p_e) valid for extrinsic semiconductors. We show then that a linear J–V_a relationship is observed in N-SI-N diodes when ${\mathbf{M}}_{\mathbf{t}}(=\frac{N_{\text{A}}}{(N_{\text{t}}-N_{\text{A}})}\frac{{\tau }_{\text{nt}}}{{\tau }_{\text{pt}}}\frac{p_{1\text{t}}}{n_{1\text{t}}})<1$ and in P-SI-P diodes when: M_t > 1. The quasi totality of the applied voltage V_a is lost across the SI layer and the electric field is constant (E ≈ V_a/L_SI). M_t < 1 characterizes a SI(N^?) layer where a strong hole depletion (p ≈ 0) across the SI bulk is associated to an “ohmic” electron current where n is constant but such that n < n_e. M_t > 1 characterizes a SI(P^?) layer where forn ≈ 0, p < p_e. On the other hand, the J–V_a characteristics of N-SI(P^?)-N diodes and P-SI(N^?)-P diodes show a saturation effect. Most of the applied voltage is now lost across the reverse biased contact and the electric field is low across the SI layer. For M_t values close to 1, we switch from a linear to a saturation regime. Equivalent relations are given for a deep acceptor compensating a shallow donor. We present results for short SI layers having lengths L_SI in the micrometer range and of the order or inferior to the ambipolar diffusion length L_Da, such layer are used as insulating layers in buried heterostructures for diode laser technology, as well as for long SI layers, L_SI ? L_Da, as used in radiation detectors technology.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.