A Novel Self-Aligned Etch-Stopper Structure With Lower Photo Leakage for AMLCD and Sensor Applications

In this letter, the authors introduce a novel self-aligned etch-stopper sidewall-contact hydrogenated amorphous silicon (a-Si : H) thin-film transistor (ESSC-TFT), which reduces the photo leakage current by more than one order of magnitude and increases the on-off ratio to seven orders of magnitude under back light illumination. Such a TFT will enable high-resolution and high-brightness liquid-crystal displays (LCDs) for next-generation TV, monitor, notebook, and mobile-phone applications. This ESSC-TFT design reduces the volume of a-Si film in which the active region can totally be shielded by the gate metal resulting in the prevention from direct back light illumination. With the sidewall contact, the hole current is reduced due to the smaller contact area between drain/source and a-Si layer. As well as the source, drain parasitic intrinsic resistance of a-Si can be also lessened by the ESSC-TFT structure. Although the defects between etched a-Si and n⁺ a-Si film may degrade the on current, the ESSC-TFT still exhibits higher on-off ratio and lower leakage than the one in traditional etch-stopper (ES)-TFT structure. The ESSC-TFT structure can be used not only for TFT-LCD application but also for the applications that demand high on-off ratio and low-leakage device, such as X-ray image sensor     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.     

一种能有效抑制背光照影响的非晶硅薄膜晶体管

提出了一种能有效抑制背光照影响的非晶硅薄膜晶体管结构。详细地分析了源、漏电极接触区和沟通区内载流子的输运特性。论述了在背光照射下,这种结构的ＴＦＴ能有铲抑制关态电流上升的机理。研究了有源层ａ－Ｓｉ：Ｈ膜层厚度对ＴＦＴ关态电流和开态电流的影响。检测辽种结构ＴＦＴ在暗态和背照射下的静态特性。     

非晶硅薄膜激光晶化及其结构分析

以射频(频率为13.6MHz)磁控溅射系统制备的非晶硅薄膜为前驱物,采用激光晶化技术实现从非晶硅薄膜到纳米晶硅薄膜的相变过程。采用拉曼光谱仪和高分辨透射电镜对激光晶化薄膜的组织结构进行了研究。结果表明:薄膜由非晶硅结构转变为微晶硅结构,微晶硅晶粒尺寸在纳米级。激光晶化存在一个最佳工艺参数,功率太高或太低都不利于晶化。     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

The Substrate Effects on Kinetics and Mechanism of Solid-Phase Crystallization of Amorphous Silicon Thin Films

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using Si₂H₆ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer (SiO₂/Si), quartz and LPCVD-oxide, and annealed at 600 °C in an N₂ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the SiO₂/Si starts from the interface between the a-Si and the substrate, so called interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.     

Comparison of the agglomeration behavior of Ag(Al) films and Ag(Au) films

It is essential to suppress agglomeration of Ag films caused by thermal treatment for their successful application as new metallization materials. Co-sputtered Ag(Al) and Ag(Au) films were investigated, with regard to their change in morphology and electrical resistivity after vacuum annealing. As a result, agglomeration of the Ag(Al) film (Al: 4.3 at.%) was not recognized even after annealing at 600 °C. However, void formation followed by de-wetting was observed for the Ag(Au) film after annealing, similar to that for a pure Ag film. The morphological change was accompanied by an increase in the resistivity of the Ag(Au) films with annealing temperature. On the other hand, the resistivity of the Ag(Al) films did not increase by annealing at temperatures from 400 to 600 °C. However, the film with the highest Al content, which was most resistive to agglomeration, had too high resistivity for use as a metallization material. By analysis of the Auger depth profile, the presence of very thin oxide layers at the surface of the film and at the interface with the substrate was confirmed for Ag(Al) films after annealing. This was considered to be the reason for the large difference in agglomeration behavior between the Ag(Au) and Ag(Al) films.     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

Amorphous-silicon-on-glass field emitter arrays

An amorphous-silicon (a-Si) field emitter array (FEA) has been fabricated on a glass substrate and characterized, At first, a 0.3-μm-thick Cr film was deposited on the glass by vacuum evaporation technique and subsequently a 1-μm-thick Si film was deposited on the Cr film by conventional RF sputtering technique with an undoped Si target at room temperature. The sputtered Si film was identified as amorphous from X-ray diffraction patterns and had a resistivity of 3-5 kΩ-cm. The FEA consists of 1-μm-high emitter tips and a gate electrode with 1.8-μm-diameter openings. This a-Si FEA with 5×5 (=25) tips exhibited a threshold voltage of 30 V and an emission current of 2 μA at a gate voltage of 100 V. Structure and emission characteristics are discussed     

Amorphous InGaZnO thin film transistors with sputtered silver source/drain and gate electrodes

The amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with sputtered silver source/drain (S/D) and gate electrodes were investigated and developed. The sputtered single-film Ag was confirmed to be unfit for the electrodes of a-IGZO TFTs because of its bad contact with a-IGZO and atom diffusion into insulators. Accordingly the sputtered Mo films were proposed to serve as the capping layers, indicating that the 20-nm-thick Mo could effectively form ohmic contact with the a-IGZO, prevent the Ag diffusion into the SiO_x, and make good adhesion to the glass substrates. The devices with multi-layer S/D and gate electrodes (Mo/Ag/Mo) were successfully fabricated, exhibiting the reasonably good performance and thus proving the application of the sputtered silver electrodes into a-IGZO TFTs was possible.     

Microstructure evolution of amorphous silicon thin films upon annealing studied by positron annihilation

Amorphous silicon (a-Si) thin films were prepared on glass substrates by plasma enhanced chemical vapor deposition (PECVD). Influence of annealing temperature on the microstructure, surface morphology, and defects evolution of the films were studied by X-ray diffraction (XRD), atomic force microscope (AFM) and positron annihilation Doppler broadening spectroscopy (DBS) based on a slow positron beam, respectively. The S parameter of the as-deposited a-Si thin film is high, indicative of amorphous state of Si film with many defects. The a-Si gradually grows into polycrystalline silicon with increasing temperature to 650 °C. For the films annealed below ~450 °C, positron diffusion lengths are rather small because most positrons are trapped in the defects of the a-Si films and annihilated there. With further rising the temperature to 600 °C, the diffusion length of positrons increases significantly due to the removal of vacancy-type defects upon annealing at a high temperature. The results indicate that the coalescence of small vacancy-type defects in a-Si thin film and the crystallization of a-Si occur around 450 °C and 650 °C, respectively.     

Novel polycrystalline silicon thin film transistors prepared by deposition from Si2H6 and subsequent annealing by NH3 plasma

This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si₂H₆ gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH₄ deposited devices. These devices were also subsequently passivated by NH₃ plasma. The NH₃ plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH₃ plasma passivation.     

高掺杂氢化非晶硅薄膜

采用低浓度硅烷,低生长速率,在PECVD系统中制得高掺杂氢化非晶硅(N~+α-Si:H)薄膜,其电导率高达5～36Ω~(-1)cm~(-1)。应用该技术制成了新型二维电子气Si/N~+α-Si∶H异质结双极型晶体管,在硅微波功率异质结双极型晶体管研制上取得重大突破。     

The effects of hydrogen on aluminum-induced crystallization of sputtered hydrogenated amorphous silicon

The effects of hydrogen on aluminum-induced crystallization (AIC) of sputtered hydrogenated amorphous silicon (a-Si:H) were investigated by controlling the hydrogen content of a-SiH films. Nonhydrogenated (a-Si) and hydrogenated (a-Si:H) samples were deposited by sputtering and plasma-enhanced chemical vapor deposition (PECVD). All aluminum films were deposited by sputtering. Hydrogen was introduced into the sputter-deposited a-Si films during the deposition. After deposition, the samples were annealed at temperatures from 200°C to 400°C for different periods of time. X-ray diffraction (XRD) patterns were used to confirm the presence and degree of crystallization in the a-Si:H films. For nonhydrogenated films, crystallization initiates at a temperature of 350°C. The crystallization of sputter-deposited a-Si:H initiates at 225°C when 14% hydrogen is present in the film. As the hydrogen content is decreased, the crystallization temperature increases. On the other hand, the crystallization initiation temperature for PECVD a-Si:H containing 11at.%H is 200°C. Further study revealed that the crystallization initiation temperature is a function, not only of the total atomic percent hydrogen in the film, but also a function of the way in which the hydrogen is bonded in the film. Models are developed for crystallization initiation temperature dependence on hydrogen concentration in a-Si:H thin films.     

Understanding the Effects of Stress on the Crystallization of Amorphous Silicon

This paper presents the results of a systematic study on the effects of stress on aluminum-induced crystallization (AIC) of plasma-enhanced chemical-vapor-deposited (PECVD) amorphous silicon (a-Si:H). To decouple the impact of stress on the AIC of a-Si:H from other factors that may affect crystallization, such as a-Si:H and aluminum deposition conditions, identical thin film structures [Al (200 nm)/a-Si:H (200 nm)] were deposited on the front surface of all samples. On the back surfaces, various amorphous silicon films were deposited to adjust the curvature of the samples and, therefore, the stress in the a-Si:H film on the front surface. It was found that tensile stress in a-Si:H can retard the AIC of a-Si:H.