Performance of A prioritized on-board baseband switch for A multiservice multibeam satellite

In this paper, we study the performance of a prioritized on-board baseband switch in conjunction with a multibeam satellite handling integrated services. The services considered for the analysis include voice, video, file transfer and interactive data. The prioritized switch uses both input and output buffering, switch speed-up as well as a two-phase head-of-line resolution algorithm, in order to reduce the buffer loss while maintaining acceptable user delays. The minimum required buffer capacity and switch speed-up for each service in a prioritized environment are found under uniform traffic conditions. It is shown that under uniform traffic conditions, only minimal buffering and switch speed-up are needed even for the lowest priority users. The performance dependence on the switch size is also substantially reduced with head of line resolution and buffering even in a prioritized environment.     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

Cell loss analysis and design trade-offs of nonblocking ATMswitches with nonuniform traffic

In practical ATM switch design, a proper dimensioning of buffer sizes and a cost effective selection of speed-up factor should be considered to guarantee a specified cell loss requirement for a given traffic. Although a larger speed-up factor provides better throughput for the switch, increasing the speed-up factor involves greater complexity and cost. Hence, it may not be cost effective to increase the speed-up factor for 100% throughput. Moreover, with a given buffer budget, an increase in the speed-up factor beyond a certain value only adds to the cell loss. The paper addresses design trade-offs existing between finite input/output buffer sizes and speed-up factor in a nonblocking ATM switch. Another important issue is the adverse effect on cell loss performance caused by nonuniform traffic (different traffic intensity and unevenly distributed routing). The paper analyzes cell loss performance of ATM switches with nonuniform traffic, and examines the effect of each nonuniform traffic parameter. The authors also provide an algorithm for effective buffer sharing that alleviates the performance degradation caused by traffic nonuniformity     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

ON IMPROVING THE DESIGN OF AN ATM SWITCH BASED ON INPUT–OUTPUT BUFFERS

We describe the development and analysis of an asynchronous transfer mode (ATM) switch architecture based on input–output buffers, a sort-Banyan network and a feedback acknowledgement (ACK) signal to be sent to the input unit. This is an input-buffer and output-buffer type of switch but with the different approach of feedback, which uses an acknowledgement feedback filter for recycling cells that lose contention at the routing network. In contrast to another design¹ which uses a merge network, a path allocation network and a concentration network at the output of the sort network to generate the acknowledgement signal, in this new proposal, the filler network has been simplified using only N filter nodes (2 × 2 switch element) and multiplexers which are placed at the feedforward of the sort network. This switch provides non-blocking, low cell loss and high throughput properties. It is designed with internal speed-up to enhance its throughput, to reduce the head of line (HOL) blocking, and to reduce the end-to-end delay.     

Analysis of a new multiaccess/switching technique for multibeamsatellites in a prioritized ISDN environment

A performance analysis to compute the packet loss, call blocking, and packet delays of a typical user in an integrated voice-data-video satellite internetworking environment is discussed. The uplink technique used is a hybrid packet/circuit switched approach of the demand assignment type, while the downlink is a time-division-multiplexing (TDM) technique. Onboard the satellite, a baseband nonblocking switch is used to route the packets from input to output ports. Various amounts of input and output buffering as well as priority rules and blocking resolution algorithms are used. The authors conduct a performance analysis for the problems at hand and identify the best ranges for the different parameters involved     

Performance study of an input and output queueing ATM switch with a window scheme and a speed constraint

In this paper, we study the performance of an input and output queueing switch with a window scheme and a speed constraint. The performance of a non-blocking ATM switch can usually be improved by increasing the switching speed. Also, the performance of a switch can be improved using a window scheme by relaxing the first-in-firstout (FIFO) queueing discipline in the input queue. Thus, one can expect that a combined scheme of windowing and a speed constraint can improve further the performance of the packet switch. Here, we analyze the maximum throughput of the input and output queueing switch with a speed constraint combined with windowing, and show that it is possible to obtain high throughput with a small increment of speed-up and window size. For analysis, we model the HOL queueing system as a virtual queueing system. By analyzing the dynamics of HOL packets in this virtual queueing model, we obtain the service probability of the HOL server as a function of output contention capabilities. Using the result, we apply the flow conservation relation to this model and obtain the maximum throughput. The analytical results are verified by simulation.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

An experimental ATM switch for BISDN studies

This paper describes the architecture, functionality and performance of an experimental ATM switch being developed at the Telecom Australia Research Laboratories as part of its investigations into the broadband ISDN. The proposed switch architecture consists of parallel omega networks preceded by a Batcher bitonic sorting network. The switching fabric has no internal cell buffering. Cell buffering is provided only on the switch outputs for cells simultaneously contending for the same output port. The switch fabric and cell buffers include mechanisms for providing prioritized servicing of queued cells and prioritized discarding of cells based on priority fields contained within the cell header. Components of the switch are currently being implemented in 2 μm CMOS VLSI.     

The design and analysis of an ATM multicast switch with adaptivetraffic controller

The paper describes several improvements to a nonblocking copy network proposed previously for multicast packet switching. The improvements provide a complete solution to some system problems inherent in multicasting. The input fairness problem caused by overflow is solved by a cyclic running adder network (CRAN), which can calculate running sums of copy requests starting from any input port. The starting point can change adaptively in every time slot based on the overflow condition of the previous time slot. The CRAN also serves as a multicast traffic controller to regulate the overall copy requests. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the CRAN in a straightforward manner. Nonuniform distribution of replicated packets at outputs of the copy network may affect the performance of the following routing network. This output fairness problem due to underflow is solved by cyclically shifting the copy packets in every time slot. An approximate queueing model is developed to analyze the performance of this improved copy network. It shows that if the loading on each output of the copy network is maintained below 80%, the average packet delay in an input buffer would be less than two time slots     

一种基于Credit的变长分组并行交换网络调度算法

该文提出了一种新的并行分组交换(PPS)网络调度算法。该算法通过在解复用器处采用以变长分组为业务分配单元的方式消除了信元的乱序问题;通过采用Credit机制进行业务分配,实现了业务到各个交换平面完全公平的分配;各个并行交换单元采用组合输入输出排队,降低了对缓存和交换平面的加速要求,同时可以充分利用现有单Crossbar网络调度算法的研究成果。文中证明了该算法对业务分配的公平性,对高速缓存的需求量以及整个网络的稳定性,仿真进一步证明了该算法具有良好性能。     

Single-stage single-switch input-current-shaping technique withreduced switching loss

In this paper, a new single-stage, single-switch input-current-shaping (S⁴ICS) technique which features substantially reduced turn-on switching loss of the switch in a S⁴ ICS flyback topology is described. In the proposed technique, the turn-on switching loss due to the discharging of the output capacitance of the switch is reduced by turning on the switch when its voltage is minimum. To achieve the turn-on loss reduction for a wide range of line and load conditions, the flyback transformer is continuously operated at the boundary of the continuous conduction mode (CCM) and discontinuous conduction mode (DCM) by employing a variable-frequency control. The performance of the new S⁴ICS flyback technique was evaluated on a 70-W (20-V/3.5-A) experimental prototype     

An analytical approach to the performance evaluation of the balanced gamma switch under multicast traffic

This paper presents the performance evaluation of a new cell‐based multicast switch for broadband communications. Using distributed control and a modular design, the balanced gamma (BG) switch features high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output‐buffered architecture. The performance is evaluated under uniform and non‐uniform traffic conditions in terms of cell loss ratio and cell delay. An analytical model is presented to analyse the performance of the multicast BG switch under multicast random traffic and used to verify simulation results. The delay performance under multicast bursty traffic is compared with those from an ideal pure output‐buffered multicast switch to demonstrate how close its performance is to that of the ideal but impractical switch. Performance comparisons with other published switches are also studied through simulation for non‐uniform and bursty traffic. It is shown that the multicast BG switch achieves a performance close to that of the ideal switch while keeping hardware complexity reasonable. Copyright © 2006 John Wiley & Sons, Ltd.     

低压低能耗应用的InGaAs／AlGaAsPHEMT单片微波SPDT开关

提出了微波频率下ＰＨＥＭＴ在作开关运用时一种简化的等效电路模型，其模型参数可从对实际ＰＨＥＭＴ芯片的在片微波测试方便地确定。对于电路中元件采用不同尺寸组合情形下所进行的开关性能（插入损耗，隔离度，输入及输出反射损耗）的模拟计算表明，与实验结果符合良好。在对串／并联ＰＨＥＭＴ型ＳＰＤＴ开关的ＣＡＤ优化设计基础上进行了ＩｎＧａＡｓ／ＡｌＧａＡｓＰＨＥＭＴ单片ＳＰＤＴ微波开关的实验研制。从研制的ＭＭＩＣ芯片上在片测试得到的结果为：对应新的个人通信频段的应用，在０～２ＧＨＺ范围内，插入损耗＜１．０ｄＢ，隔离度＞５０ｄＢ，输入及输出反射损耗均优于２４ｄＢ。研制的这种高性能单片开关还可在低至－２．０Ｖ的控制电压下工作。     

Analysis of nonblocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation     

Performance of ATM Switch Based on Bifurcated Output Queuing

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On Guaranteed Smooth Switching for Buffered Crossbar Switches

Scalability considerations drive the evolution of switch design from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, CICQ switches with credit-based flow control face new challenges of scalability and predictability. In this paper, we propose a novel approach of rate-based smoothed switching, and design a CICQ switch called the smoothed buffered crossbar or sBUX. First, the concept of smoothness is developed from two complementary perspectives of covering and spacing, which, commonly known as fairness and jitter, are unified in the same model. Second, a smoothed multiplexer sMUX is designed that allocates bandwidth among competing flows sharing a link and guarantees almost ideal smoothness for each flow. Third, the buffered crossbar sBUX is designed that uses the scheduler sMUX at each input and output, and a two-cell buffer at each crosspoint. It is proved that sBUX guarantees 100% throughput for real-time services and almost ideal smoothness for each flow. Fourth, an on-line bandwidth regulator is designed that periodically estimates bandwidth demand and generates admissible allocations, which enables sBUX to support best-effort services. Simulation shows almost 100% throughput and multi-microsecond average delay. In particular, neither credit-based flow control or speed-up is used, and arbitrary fabric-internal latency is allowed between line cards and the switch core, simplifying the switch implementation.     

Two-dimensional round-robin schedulers for packet switches withmultiple input queues

Presents a new scheduler, the two-dimensional round-robin (2DRR) scheduler, that provides high throughput and fair access in a packet switch that uses multiple input queues. We consider an architecture in which each input port maintains a separate queue for each output. In an N×N switch, our scheduler determines which of the queues in the total of N² input queues are served during each time slot. We demonstrate the fairness properties of the 2DRR scheduler and compare its performance with that of the input and output queueing configurations, showing that our scheme achieves the same saturation throughput as output queueing. The 2DRR scheduler can be implemented using simple logic components, thereby allowing a very high-speed implementation     

一种输入输出排队交换机中分布式分组调度方法的研究

针对采用共享缓存(shared memory)做为交换机构(switching fabric)的输入输出排队交换机,该文给出了一个分布式分组调度方法DHIOS(Distriduted Hierarchical Ingress and OutputScheduling)并做了详细的仿真。表明DHIOS可以支持变长分组,能够确保业务流的QoS,性能优良。     

星上交换系统输入缓存调度算法

为改善星上交换系统的性能,该文提出了一种新的输入缓存调度算法。该算法基于Crossbar交换结构,采用了串行调度思想,在兼顾每个端口公平性的基础上调整了输出端口的仲裁策略,增加了端口匹配的概率。该算法大大减小了调度时延和丢失率。分析与仿真结果表明,该算法在平均调度时延和信元丢失率等方面的性能指标均优于已有算法而且实现复杂度不增加。