Methods of separation of semiconductor devices by reliability with the use of a low-frequency noise and X-ray irradiation

Methods of the separation of semiconductor devices (SDs) by reliability with the use of parameters of low-frequency (LF) noise under the effect of X-ray irradiation are considered. Different methods of the separation of SDs by reliability depending on their constructive features are suggested.     

基于低频噪声检测的光耦器件可靠性频域筛选新方法

针对光耦器件的可靠性筛选,本文提出全频段阈值筛选方法检测光耦器件内部低频噪声。根据光耦器件内部的低频噪声完成光耦器件可靠性的筛选。实验中利用光耦器件测试系统检测200只光耦器件内部的低频噪声,计算这200只光耦器件全频段平均噪声谱,确定筛选阈值,再根据光耦器件可靠性分类标准,判断被测器件可靠性等级。     

Impact of advanced processing modules on the low-frequency noise performance of deep-submicron CMOS technologies

Fundamental studies related to the low-frequency (LF) noise performance in semiconductors started more than 40 years ago. In 1957, McWhorter published the first model for the 1/f noise in semiconductors, which is still in use. Whereas for many decades LF noise studies were mainly of fundamental and theoretical interests, in recent years, LF noise characterisation has become a very valuable diagnostic technique for the development of semiconductor materials and devices. Especially, the use of noise characterisation as a tool for reliability predictions has triggered the semiconductor engineering society. Not only the silicon starting material, but also many of the used process modules have a strong impact on the noise performance. This trend is becoming even more pronounced for the advanced deep-submicron technologies. For analog applications of scaled technologies, LF noise may even act as a showstopper. This review, therefore, focuses on the impact of advanced processing on the low-frequency noise behaviour. Both front- and back-end process modules are discussed.     

Random telegraph signal currents and low-frequency noise injunction field effect transistors

The detailed study of random telegraph signal (RTS) currents and low-frequency (LF) noise in semiconductor devices in recent years has confirmed their cause and effect relationship. In this paper we describe the physical mechanisms responsible for RTS currents in any device. The methods for calculating the amplitudes and characteristic times of the RTS currents produced by traps with known electrical characteristics and locations are described. The noise spectra in junction field effect transistors (JFET's) resulting from traps in the silicon or the oxide are derived as a function of basic device parameters, operating conditions and temperature. Experimental results verifying the predictions of the models are presented     

Robust, versatile, direct low-frequency noise characterization method for material/process quality control using cross-shaped 4-terminal devices

Low frequency (LF) noise measurement is a very sensitive tool for device quality and reliability monitoring. Despite of its potential interest, there are up to now relatively few LF noise studies combined and compared to standard reliability/quality analysis. One of the reasons is the difficulty to implement LF noise measurement on automatic wafer level testing. In this paper we promote a method using cross shaped 4 terminal devices (Hall crosses). The implementation of this method and its advantages over conventional noise measurement methods are described. This method, compatible with on-wafer probe testing, is of particular interest for material/processes quality control purposes especially for less mature material such as AlGaN/GaN Heterostructures.     

基于加速退化试验的模拟IC寿命评估研究

为解决高可靠性、长寿命模拟集成电路的寿命评估问题,结合半导体器件退化失效的特点,提出了基于加速退化试验的模拟集成电路寿命评估方法。在此基础上,以某型电压基准模拟IC为研究对象,通过对退化数据的分析研究,获得了其在正常工作应力下的寿命数据。     

Effect of gamma irradiation on the low-frequency (1/̷) noise of linear ics: Reliability physics study

Linear integrated circuits IC 709 and 741 were irradiated by gamma rays using cobalt-60 source. Low-frequency noise was measured for these ICs before and after irradiation dose levels 10⁴, 10⁵, 10⁶ and 5 × 10⁶ R. In general IC 741s appeared to be more noisy than IC 709s. The noise levels increase substantially in the case of IC 741 after gamma irradiation of 10⁶ R. Comparative measurement results are presented in this article. These results may be useful to correlate radiation as a defect producing stress, mode and type of failures and reliability of linear ICs.     

FET noise sources and their effects on amplifier performance at low frequencies

In this brief review paper analytical results concerning the low-frequency (LF) amplifier noise performance of FET's are presented. The effects of interaction between the device basic noise sources, the small-signal model parameters, and the signal source admittance parameters are clearly indicated. The noise performance is found to be essentially determined by the effective surface-state density and the gate insulator thickness product (N_{ss}t_{ox}) in the case of MOSFET's, whereas in the case of JFET's, this is determined by the bulk density of impurity and/or defect generation-recombination (g-r) centers within the depletion region and the half-channel height squared product (N_{TT}a^{2}). Although an increase in the gate electrode area can reduce the equivalent gate noise resistance, this does not improve the noise performance of the device. Quantitative results based on typical device parameters are graphically presented with proper indications as to the upper limit of the LF range, the excess minimum noise figure, and the frequency range within which the noise figure remains below 3 dB level for specified source resistance values. The effects of gate leakage current on the noise performance of JFET's are included in these results.     

Reliability prediction for TFBGA assemblies

One of the key hot topics in dense large scale integration packaging technologies is to reduce the thermomechanical stress caused by a mismatch of coefficients of thermal expansion among material employed. Nearly all manufacturers of portable electronics products perform several kinds of physical tests in the development cycle to evaluate reliability of the products. In this paper, results obtained by accelerated thermal and power cycling tests by using thin fine pitch gall grid array (TFBGA) packages are reported. Power-cycling stands for a lifetime acceleration method which is close to the real environmental conditions of many electronic products. For this purpose, a set of TFBGA thermal test packages were designed and manufactured for reliability assessment of solder joint interconnections. The assemblies consisted of an array of polysilicon resistors surrounding a sensing diode for accurate temperature measurements. The package uses a qualified bill of materials including a 36-mm/sup 2/ dummy die. Each assembly was designed to perfectly reproduce the thermomechanical behavior of the mass production packages by several semiconductor manufacturers. This package is used in telecom wireless application where it offers high density input/output solution for advanced application-specific integrated circuit (IC) devices a system on chip ICs. Both experiments and simulations were carried out to locate the position of the most critical parts. Complexity of structural package characteristics was examined by using finite-element method modeling methodology. A strain energy based model was employed to locate the most vulnerable parts in the package and predict failure rates.     

高速数字电路相位噪声测试研究

对高速数字电路相位噪声测试技术进行了探索.利用直接频谱仪法、鉴相器法、鉴频器法等相位噪声测试方法,通过阻抗匹配等合理的测试设计,开发出测试系统,对高速数字电路相位噪声进行了测试研究,获得了准确的测试数据,有效地表征了电路实际性能.     

On the performance of objective quality metrics for lightfields

Lightfield (LF) technology has attained significant attention in recent years due to its capability to capture much richer textural and geometric information in the scene compared to the classical 2D representation. The resampling and compression operations on LFs often lead to visual quality degradation, thus, sophisticated visual quality assessment methods play a crucial role to ensure a pleasant viewing experience. To this end, it is necessary to examine the performance of quality assessment methods for LF contents. The paper provides a comprehensive study on the reliability of various objective algorithms for LF quality prediction. Three subjectively-annotated LF data sets were selected and an extensive quality estimation analysis has been conducted using several objective quality assessment methods. In total, 250 LFs (more than 48000 perspective images) were evaluated. The results were compared against human opinion scores using various correlation indices and their statistical significance. Next, a decision-making strategy was adopted to choose the most reliable quality metrics for evaluation of LFs and finally, a metric fusion framework was proposed to further improve the quality prediction accuracy. To best of our knowledge, the benchmark and the analytical methodologies used in this paper are the most comprehensive study on the objective quality assessment methods for LF application.     

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.     

基于生物启发的半导体器件可靠性免疫系统研究

受生物免疫系统基本原理的启发，提出了半导体器件可靠性免疫系统的概念。在介绍半导体器件的过激噪声和其内部不同缺陷之问的关系的基础上，阐述了利用噪声评估器件可靠性的原理及优点。借鉴生物免疫系统，较为详细的介绍了人工免疫系统的相关机理，并给出了半导体器件可靠性免疫系统内抗原（过激噪声）、淋巴细胞（判据）的表现形式，淋巴细胞对不可靠器件的识别过程等。实验结果表明：该方法具有快速，可靠等优点，并具有很好的适应性。     

Laplace-DLTS method with the regularization parameter chosen from the L curve

The Deep Level Transient Spectroscopy (DLTS) method is one of the basic methods widely used for determining the parameters of defects giving rise to deep levels in the band gap of a semiconductor material. It is proposed using the L-curve approach when choosing the regularization parameter in the Laplace-DLTS method for the exclusion of uncontrolled errors and an increase in reliability of obtained results. The potential of the method is demonstrated by the numerical analysis of the modeling relaxation signal, which contains three exponential functions with almost identical values of parameters and a small noise component. It is shown that the proposed variant of the Laplace-DLTS with using the L curve for choosing the regularization parameter or the LL-DLTS has a higher reliability in comparison with the Laplace-DLTS method when choosing the regularization parameter by residual.     

基于低频噪声检测的电力MOSFET可靠性分析

针对变电所中通信电源的核心器件电力金属氧化物半导体场效应晶体管(power MOSFET,P-MOSFET)在大功率、强电流下易损坏、故障率高,直接影响电力通信业务的安全稳定运行的问题,提出了一种基于低频噪声检测的可靠性分析方法.利用互功率谱测量方法检测P-MOSFET内部的本征低频噪声,根据频段阈值法的拐点噪声谱,确定P-MOSFET筛选的上下限阈值大小,建立了P-MOSFET的1/f噪声功率谱密度及其阈值的对应关系式.实验结果表明,与传统的有损检测法相比,该方法能够有效评估P-MOSFET的三种可靠性等级,提高了可靠性筛选的准确率,为其他晶体管的可靠性评估提供了参考.     

Low-frequency noise in modern bipolar transistors: impact ofintrinsic transistor and parasitic series resistances

In modern submicrometer transistors, the influence of the internal base and emitter series resistances, on both the I-V characteristics and the LF noise at higher bias currents, becomes important. In this paper expressions are presented for the LF noise in transistors, where the influence of the series resistances has been taken into account. The expressions have been compared with recent experimental results from the literature obtained from modern submicrometer (heterojunction) bipolar transistors. At low forward currents the LF noise in such transistors is determined by spontaneous fluctuations in the base and collector currents. In most transistors at higher forward currents, the parasitic series resistances and their noise become important     

Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test

Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-/spl mu/m CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.     

Secure split test techniques to prevent IC piracy for IoT devices

Globalization of semiconductor manufacturing and related activities has led to several security issues like counterfeiting, IP infringement and cloning etc. Counterfeiting not only affects the business and reputation of semiconductor vendor, it will affect the reliability of critical applications. Internet of Things (IoT's) is an emerging application area for semiconductors in which security is a prime concern. Identity or authentication of a device in the network of millions of devices in IoT's is very important. In this paper, we present Secure Split Test with functional testing capability (SSTF) scheme to mitigate the counterfeits coming out from untrusted foundries. The SSTF is suitable for low cost/low end devices. To address the identity management issue in IoT's and counterfeiting of ICs, a Physical Unclonable Function based SSTF (PUF-SSTF) is presented. PUF-SSTF is suitable for ICs targeted to use in smart phones and IoT ‘s. PUF-SSTF is a security solution to address: mitigating the counterfeit ICs coming out from untrusted foundries, identity management in IoT's and licensing the device features, which will benefit the fabless semiconductor vendors for licensing and entitlement management. The proposed SSTF and PUF-SSTF techniques are implemented in both ASIC and FPGA and security analysis is performed. The security analysis results are in par with earlier secure split test techniques like Connecticut Secure Split Test (CSST). The proposed techniques will create the comprehensive secure supply chain solution, which will benefit fabless semiconductor vendor and end-user.     

Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration

Coupling noise induced by through silicon vias (TSVs) is expected to be a major concern for three dimensional integrated circuits (3-D ICs) system design. Using equivalent electrical parameters for carbon nanotube (CNT) TSV interconnects, a lumped crosstalk noise model is introduced to capture the TSV-to-TSV coupling noise in CNT via based 3-D ICs and validated with multiple conductor transmission line (MTL) simulation results. The effect of geometrical and material parameters involved on the noise transfer function and peak crosstalk noise, such as insulation thickness, TSV–TSV spacing, TSV height, TSV radius, substrate conductivity and metallic CNT density, is investigated with the proposed model. Simulation results show that the TSV coupling can be divided into three frequency behavior regions. Three approaches using driver sizing, grounded vias shielding and air gap-based silicon-on-insulator (SOI) technique are proposed to mitigate TSV crosstalk coupling noise. The proposed approaches are demonstrated in frequency- and time- domain simulations. They provide the reduction in full-band noise transfer function by an average of 11.71 dB, 24.85 dB and 3.46 dB, and the decrease in 1 GHz peak noise voltage by 53.24 mV, 40.72 mV and 15.1 mV.     

基于人工神经网络的IC互连可靠性研究

鉴于有限元分析耗时耗资源的缺点,为了加速集成电路的互连可靠性分析,提出将传统的有限元建模和人工神经网络(ANN)建模技术结合来实现IC的建模和仿真分析.采用有限元ANSYS参数化设计语言(APDL)实现IC三维模型的自动构建和原子通量散度(AFD)计算,之后通过对计算所得的可靠性数据进行训练和测试,采用神经网络技术对模型的输入输出关系进行建模,使模型达到足够高的精度.神经网络模型构建好之后,可以在短时间产生一个可靠性数据库.通过对数据的统计分析可以得到电路在不同条件下的互连可靠性,进而分析各因素对电路互连可靠性的影响,为集成电路的互连可靠性分析和设计提供重要指导.