Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V_pp differential input is improved from ?42 dB to ?55 dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of ?53 dB for 0.4V_pp differential input. It consumes 345 μw from 1.0 V single supply. Theoretical and simulated results are in good agreement.     

Low-voltage low-power FGMOS based VDIBA and its application as universal filter

This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.     

On design of a novel class of selective CIC FIR filter functions with improved response

The Cascaded-Integrator-Comb (CIC) filter is a non-recursive (FIR) filter which is multiplier free, consisting only of two building blocks (simple integrator stage and simple comb filter stage) and has a linear phase. This paper summarizes some key points of classical CIC filters and proposes a novel class of CIC FIR filter functions. A novel class of CIC filter functions maintains simplicity of FIR filters by avoiding the multipliers, but shows excellent performances in term of insertion loss in stopband and selectivity with respect to conventional CIC filters. A set of simulations along with illustrative examples is conducted in order to compare the attenuation characteristics of the classical CIC filter functions and the proposed novel class of selective CIC FIR filter functions. For the same level of a constant group delay τ = 45.5 s, a classical CIC filter function has insertion loss of 166.3 dB, and designed novel filter function has a higher level of insertion loss 206.55 dB.     

Design of selective CIC filter functions

The aim of this letter is to provide graphs which can be used to design a novel class of selective CIC (Cascaded-Integrator–Comb) filters given insertion loss specification. The goal is to choose the free integer filter parameters such that the filter function yields a desired frequency response. To determine the filter parameters needed to satisfy the desired specifications, one can use the graphs of normalized passband and stopband cut-off frequencies versus filter order N. Two graphs, one for maximum attenuation in the passband and one for minimum attenuation in the stopband, are given here. Achieved improvement of performances of the novel class of CIC filter functions over the classical CIC filters is also given. In case of N = 7, the novel class of CIC filter functions gives improvements of 27.68 dB, 47.29 dB and 66.53 dB for different values 1, 2 and 3 of free parameter L, respectively.     

Log-domain high-order low-pass and band-pass filters

Continuous time current-mode high-order low-pass and band-pass filters based on the log-domain concept are presented in this paper. The passive RLC ladder networks are used as the prototype to achieve the proposed filter by simulating the RLC network synthesis method. The achieved filters have inherited the good sensitivity performance from the RLC passive prototype. Fifth-order RLC ladder low-pass filter and sixth-order RLC ladder band-pass filter are used as prototypes and the signal flow graph (SFG) technique is used for the synthesis. The SFG can identify group of integrators and several signal paths. Log-domain lossy and lossless integrators based on BJT technology are deployed to achieve the integrators for realization of proposed filters. The simulations were carried out and the results exhibited several features which are in agreement with the RLC prototype. The frequency response of filters along 100 kHz to 10 MHz can be electronically tuned through 5–500 µA of bias currents. The THD lower than 1% of LP and BP filters were measured at 10 MHz input. The multi-tone tested was included in the paper for verifying the performance of proposed LP and BP filters. The intermodulation distortions around −50 dB and −60 dB were also investigated for the proposed LP and BP filters.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

Capacitorless digitally programmable fractional-order filters

Novel topologies of fractional-order filters, implemented using the internal gate-source capacitance of MOS transistors, are introduced in this paper. This has been achieved using current-mirrors as active elements, resulting into resistorless realizations due to the employment of the small-signal transconductance parameter of the MOS transistor. This also offers the capability for electronic tuning of the frequency characteristics of the derived filter structures. The evaluation of the proposed technique has been performed through the design of a generalized fractional-order filter, which is also digitally programmed in such way that the four standard filter functions are offered. The behavior of the filter has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Improving GBW product on CMOS operational transconductance amplifiers by interleaved feedforward paths

This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.     

An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques

A wideband common-gate (CG) low-noise amplifier (LNA) with dual capacitor cross-coupled (CCC) feedback and negative impedance techniques is presented for multimode multiband wireless communication applications. Double CCC technique boosts the input transconductance of the LNA, and low power consumption is obtained by using current-reuse technique. Negative impedance technique is employed to alleviate the correlation between the transconductance of the matching transistors and input impedance. Meanwhile, it also allows us to achieve a lower noise figure (NF). Moreover, current bleeding technique is adopted to allow the choice of a larger load resistor without sacrificing the voltage headroom. The proposed architecture achieves low noise, low power and high gain simultaneously without the use of bulky inductors. Simulation results of a 0.18-μm CMOS implementation show that the proposed LNA provides a maximum voltage gain of 25.02 dB and a minimum NF of 2.37 dB from 0.1 to 2.25 GHz. The input-referred third-order intercept point (IIP3) and input 1-dB compression point (IP_1dB) are better than –7.8 dBm and –19.2 dBm, respectively, across the operating bandwidth. The circuit dissipates 3.24 mW from 1.8 V DC supply with an active area of 0.03 mm².     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

Multipath recycling method for transconductance enhancement of folded cascade amplifier

A multipath recycling method to enhance transconductance of the folded cascode amplifier is presented in this paper. The proposed method utilizes two idle paths to conduct small signal current, which leads to significant enhancement of transconductance compared to conventional folded cascade structure. Moreover, the improved performance is almost at no expense of power dissipation. The proposed multipath recycling and the conventional amplifiers are all designed in UMC 0.18 μm CMOS technology. Simulation results demonstrate that the transconductance of the proposed amplifier is improved by 450% and dc gain enhances 16 dB when compared with the folded cascode counterpart.     

A 10 GHz low phase-noise CMOS voltage-controlled oscillator using dual-transformer technology

A novel low phase-noise differential Colpitts VCO by using transformer feedback technology is presented in this paper. This work demonstrates a simple differential topology with dual-transformer approach to reduce phase-noise at low DC power consumption. A symmetrical circuit layout can be realized easily by transformers and a commonly cross-coupled structure is not adopted herein because cross couple feedback path is also a serious parasitic effect more at 10 GHz operation. Therefore, dual-transformers provide a compact feedback path and DC feed path simultaneously. Consuming a DC power of 8 mW in the VCO core, the circuit exhibits a phase-noise of ?115 dBc/Hz at offset frequency of 1-MHz and the figure of merit value is ?184.1 dBc.     

Compact differential bandpass filter with a narrow notched band using APCL structure suitable for UWB application

A compact differential band pass filter with asymmetric parallel-coupled lines (APCL) and center frequency of 5.6 GHz is proposed in this paper. The APCL suppresses unwanted RFID signals by introducing a fully tunable notched band at 6.8 GHz. By combining the concept of transmission matrix with modal analysis and extracting a novel model for symmetric three parallel coupled lines (SPCL), role of each resonant frequency is clearly explained. Measurement results in the differential mode show a pass band from 3.1 to 8.1 GHz and a wide stop band from 9.1 to 16 GHz with attenuation of more than 20 dB. In addition, S₂₁ in common mode is lower than −10.5 dB over the pass band.     

A highly linear bulk-driven CMOS OTA for continuous-time filters

In this paper we present a bulk-driven CMOS triode-based fully balanced operational transconductance amplifier (OTA) and its application to continuous-time filters. The proposed OTA is linearly tunable with the feature of low distortion and high output impedance. It can achieve wide input range without compromising large transconductance tuning interval. Using a 0.18 μm n-well CMOS process, we have implemented a third-order elliptic low-pass filter based on the proposed OTA. Both the simulation and measurement results are reported. The total harmonic distortion is more than −45 dB for fully differential input signals of up to 0.8 V peak–peak voltage. A dynamic range of 45 dB is obtained under the OTA noise integrated over 1 MHz.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

A novel architecture for improving slew rate in FinFET-based op-amps and OTAs

A new architecture for improvement of slew rate (SR) of an op-amp or an operational transconductance amplifier (OTA) in FinFET technology is proposed. The principle of operation of the proposed architecture is based on a set of additional current sources which are switched on, only when OTA should provide a high current, usually for charge or discharge of large load capacitor. Therefore, the power overhead is less compared to conventional high SR designs. The commonly used two-stage Miller-compensated op-amp, designed and optimized in sub 45 nm FinFET technology with 1 V single supply voltage, is used as an example for demonstration of the proposed method. For the same FinFET technology and with optimal design, it is shown that the slew rate of the op-amp is significantly improved. The slew rate is improved from 273 to $5590\mathrm{V}/\mathrm{\mu }\mathrm{s}$ for an input signal with a rise time of 100 ps. The other performance measures such as gain and phase margin remain unchanged with the additional circuitry used for slew rate enhancement.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Fabrication of a planar water gated organic field effect transistor using a hydrophilic polythiophene for improved digital inverter performance

A planar water gated OFET (WG-OFET) structure is fabricated by patterning gate, source and drain electrodes on the same plane at the same time. Transistor output characteristics of this novel structure employing commercial regioregular poly(3-hexylthiophene) (rr-P3HT) as polymer semiconductor and deionized (DI) water as gate dielectric show successful field effect transistor operation with an on–off current ratio of 43 A/A and transconductance of 2.5 μA/V. These output characteristics are improved using P3HT functionalized with poly(ethylene glycol) (PEG) (P3HT-co-P3PEGT), which is more hydrophilic, leading to on–off ratio of 130 A/A and transconductance of 3.9 μA/V. Utilization of 100 mM NaCl solution instead of DI water significantly increases the on–off ratio to 141 A/A and transconductance to 7.17 μA/V for commercial P3HT and to 217 A/A and to 11.9 μA/V for P3HT-co-P3PEGT. Finally, transistors with improved transconductances are used to build digital inverters with improved characteristics. Gain of the inverters employing P3HT and P3HT-co-P3PEGT are measured as 2.9 V/V and 10.3 V/V, respectively, with 100 mM NaCl solution.