A highly linear CMOS transconductance amplifier in 180?nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180?nm CMOS process technology with 1.8?V power supply. Simulation results show third order harmonic distortion (HD ₃) of ?70?dB for 600?mV_pp input signal. For 1% transconductance variation the linear range is about 1.2?V_pp. The input referred noise of the transconductor is $70\,\hbox{nV}/\sqrt{\text {Hz}}$ at 10?MHz. The quiescent power consumption is only 450???W.     

A linear compact tunable transconductor for Gm-C applications

A CMOS highly linear voltage-controlled transconductor suitable for Gm-C filter design is presented. The control loop to program the transconductance maintains the input transistors in triode region with a compact topology. Measurement results for the transconductor fabricated in a 0.5-??m CMOS technology feature a spurious-free dynamic range (SFDR) of 72?dB for 1 V_pp differential inputs at 1?MHz. The voltage to current converter ensures a high linearity level for a wide transconductance range. Functionality of the transconductor is shown in a fifth-order Gm-C tunable complex filter well suited for a dual-mode Bluetooth/Zigbee transceiver.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

A wideband balun–LNA

In this paper a wideband Low Noise Amplifier (LNA) is introduced which also converts the single-ended input to differential signal at the output. It is based on common-source amplifier with active-feedback to provide input matching. The proposed amplifier has the input matched from 500 MHz to 2.5 GHz. It achieves the maximum voltage gain of 24 dB in this band, while the minimum noise figure (NF) is 2.35 dB. The simulated OIP3 of this amplifier is equal to 21 dBm. The LNA has been designed and simulated in a 0.18 μm CMOS process.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

Miniaturized microstrip bandpass filter designed using rectangular dual spiral resonator

A miniaturized microstrip bandpass filter based on a rectangular dual spiral resonator (DSR) is proposed in this paper. The rectangular DSR bandpass filter is centered at 3.65 GHz to suit for Wireless LAN (IEEE802.11y) application. The proposed filter offers transmission zero at the high side of out-of-band response. Across the bandwidth, the measured minimum insertion loss is about 1.7 dB, while the measured return loss is better than 19 dB. Measurement results are good agreement and closed to the simulated ones. The total circuit size of the miniaturized bandpass filter is about 0.145λ_g by 0.135λ_g, where λ_g is the guided wavelength at 3.65 GHz.     

Low-voltage improved accuracy Gaussian function generator with fourth-order approximation

An original realization of a CMOS Gaussian function generator is presented. The proposed method is based on a new approximation function that is able to fourth-order match the Gaussian function. The current-mode operation of the circuit strongly reduces the technological-caused errors and the errors introduced by temperature variations, with the result of an important increasing of the accuracy for the squaring circuit that represents the functional core of the Gaussian generator (0.1%). Additionally, the bandwidth of the generator is increased as a result of its current-mode operation. Because of the utilization of the new fourth-order approximation function, the deviation from the ideal Gaussian function is smaller than 1 dB for an extended range of the input variable. The circuit is designed for implementing in 0.18 μm CMOS technology, its proposed architecture being compatible with a low-voltage operation (V_DD=1 V). The proposed Gaussian function generator based on the new approximation function allows to extend its capability of generating any continuous mathematical functions, this feature being obtained by changing the approximation function coefficients.     

A Gm-C continuous-time anti-alias filter for UWB analog front-end

A proposed constant drain-source transconductor topology is designed to keep linearity at high frequency. By using the proposed operational transconductance amplifier as a building block, a fourth-order low-pass filter is realized. The filter was fabricated in 0.18 μm CMOS technology and feathers a 250 MHz cutoff frequency. The measured IM3 performance is ?36 dB at 0.6 V_pp input swing and the power consumption is 22 mW.     

0.4-V bulk-driven differential-difference amplifier

A new solution for an ultra-low-voltage, low-power, bulk-driven fully differential-difference amplifier (FDDA) is presented in the paper. Simulated performance of the overall FDDA for a 50 nm CMOS process and supply voltage of 0.4 V, shows dissipation power of 31.8 μW, the open loop voltage gain of 58.6 dB and the gain-bandwidth product (GBW) of 2.3 MHz for a 20 pF load capacitance. Despite the very low supply voltage, the FDDA exhibits rail-to-rail input/output swing. The circuit performance has also been tested in two applications; the differential voltage follower and the second-order band-pass filter, showing satisfactory accuracy and dynamic range.     

Enhanced source-degenerated CMOS differential transconductor

A simple technique to improve the output resistance and the linearity of a source-degenerated differential CMOS transconductor is presented, useful even under low supply voltage. It combines the utilization of a super-transistor as a unity-gain buffer and the use of the weak inversion region to optimize a regulated cascode source. Using a standard 0.13 μm CMOS technology with 1.5 V supply voltage, simulation results show the transconductor attains more than 1 GΩ as differential output resistance and a third-order harmonic distortion factor less than −110 dB at 1 kHz for a 0.35 V_pp differential input signal. Other performances are 126 μW power consumption and 65 MHz bandwidth.     

A new ultra low-power,universal OTA-C filter in subthreshold region using bulk-drive technique

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans-resistance and trans-conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I_a = 50 nA, I_b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans-conductance (g_m) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Compact differential bandpass filter with a narrow notched band using APCL structure suitable for UWB application

A compact differential band pass filter with asymmetric parallel-coupled lines (APCL) and center frequency of 5.6 GHz is proposed in this paper. The APCL suppresses unwanted RFID signals by introducing a fully tunable notched band at 6.8 GHz. By combining the concept of transmission matrix with modal analysis and extracting a novel model for symmetric three parallel coupled lines (SPCL), role of each resonant frequency is clearly explained. Measurement results in the differential mode show a pass band from 3.1 to 8.1 GHz and a wide stop band from 9.1 to 16 GHz with attenuation of more than 20 dB. In addition, S₂₁ in common mode is lower than −10.5 dB over the pass band.     

Low-power MicroVrms noise neural spike detector for implantable interface microsystem device

In this paper, an ultra-low-power and low-noise spike detector is proposed for massive integration in the implantable multichannel brain neural recording device. The detector circuit with nonlinear energy operator (NEO) algorithms achieves the spike detecting from action potential including complex noise. The spike detector circuit consists of a differentiator with a fully-differential structure and a multiplier based on CMOS translinear using sub-threshold technique. The differentiator has the steepness of a transmission function with frequency +20 dB/dec, frequency response from 10 Hz to 10.5 kHz. The linear range of multiplier is from −0.9 V to 0.9 V at V_DD = ±1.65 V. The spike detector is implemented in 0.35 μm technology with fully-CMOS process. One detector die size is 0.0187 mm² and its total current consumption of 825 nA. As is demonstrated by measured results, the proposed circuit has detected the instantaneous energy of the input real spike signals well, which the noise of small than 218 μV_rms over a nominal bandwidth of 500–10.5 kHz.     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

Low-voltage,low-power Vt independent voltage reference for bio-implants

Biomedical electronics trends focus mainly on portability, miniaturization, connectivity, humanization, security and reliability. In this scenario, digital, low-cost CMOS technology plays a key role, especially in implementing complex systems into small devices with no batteries that can even be implanted in humans. Due to patient safety, the implanted devices are faced with challenges: device operation temperature and the RF power link must be kept extremely low.By using proper topologies, the whole system can be designed to operate in low-voltage and low-power modes to maintain low temperature and avoid tissue thermal hazards. In this paper, a voltage reference is proposed which can operate at as low as 500 mV with power consumption less than 100 nW. Furthermore, the proposed topology, based on composite transistors operating in weak inversion, shows a good rejection to threshold voltage V_t, which is an inherent CMOS dispersion parameter. Simulation results using the process corners show that the V_t dependence can be reduced to less than ±2% (3σ) at the body temperature and the PSRR can be as large as 65 dB for higher frequencies. One of the key features of the circuit is its simple design.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

A broadband Low Noise Amplifier with built-in linearizer in 0.13-µm CMOS process

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.