一种基于单电子隧穿结和MOS晶体管的混合随机数发生器

提出了一种新颖的单电子随机数发生器(RNG).该随机数发生器由多个单电子隧穿结(MTJ)以及单电子晶体管(SET)/MOS管混合输出电路组成.MTJ被用于实现一个高频率的振荡器.它利用了电子隧穿的物理随机性得到了很大的振荡频率漂移.SET/MOS管输出电路放大并输出MTJ振荡器的输出信号.该信号经过一个低频信号采样后,产生随机数序列.所提出的随机数发生器使用简单的电路结构产生了高质量的随机数序列.它具有简单的结构,输出随机数的速度可以高达1GHz.同时,该电路还具有带负载能力以及很低的功耗.这种新颖的随机数发生器对未来的密码和通讯系统具有一定的应用前景.     

一种采用饱和区MOS管作调节开关的电荷泵

为了得到稳定的输出电压,电荷泵电路需要通过负反馈系统进行控制.在传统的"Skip"模式电荷泵中,采用工作在线性区的MOS管做开关,通过控制振荡器来调节输出电压,但这种方式会产生较大的输出电压纹波.设计了一种采用饱和区MOS管作调节开关的电荷泵,通过控制饱和区MOS管的导通电阻来调节电荷泵的输出电压.它工作在占空比为50%的方波信号下,具有很低的输出电压纹波(37mV).     

具有自动稳幅功能的软激励C类大功率射频振荡器

介绍了一种具有自动稳幅功能的软激励C类大功率射频振荡器。大功率射频振荡器已经广泛应用于电力电子、射频电源、低温等离子体、高频感应加热等领域。该大功率射频振荡器能够输出较高的输出电压和输出功率,并且通过对输出电压采样控制MOS管的静态工作点,稳定输出电压;另外,该设计电路起振时工作在AB类状态,稳定工作时在自动稳幅电路的作用下进入C类工作状态,实现了C类射频振荡器的软激励。最后通过仿真和实物电路测试了电路性能,并给出了振荡器输出电压、输出功率与MOS管工作状态关系的经验公式。     

MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6 .91k Hz/g.     

MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6.91kHz/g.     

基于SET/MOS混合结构的译码器电路的设计

基于SET的I-V特性以及SET与MOS管互补的特性,以MOS管的逻辑电路为设计思想,首先提出了一个SET/MOS混合结构的反相器,进而推出或非门电路,并最终实现了一个唯一地址译码器.通过SET和MOS管两者的混合构建的电路与纯SET实现的电路相比,电路的带负载能力增强;与纯MOS晶体管实现的电路相比,电路同样仅需要单电源供电,且元器件数目得到了减少,电路的静态功耗大大降低.仿真结果验证了电路设计的正确性.     

一种幅频稳定的正弦信号发生器

提出了一种简易的正弦信号发生器结构,电路前级为一个频率稳定的张弛振荡器,后级为一个三角-正弦信号转换器,利用一种新颖的两级温度系数互补原理,获得了不随温度变化的稳定的输出幅度.该信号发生器工作在±15 V电源电压下,频率稳定性为98×10-6/℃,幅度稳定性0.05 μA/℃.该振荡器已成功集成到线性可变差动变压器(LVDT)的信号调理芯片中.     

应用于UHF RFID标签的低功耗真随机数发生器

设计了一种基于振荡采样法的真随机数发生器.针对UHF RFID标签芯片功耗低、面积小的特点,利用简单有效的电路结构增强发生器的随机性.采用频率受控的被采样数据振荡器与采样时钟异或后形成初步随机数,并增加异或链输出负反馈结构,有效提高了输出序列中"0""1"分布的均匀性,降低了序列的自相关性.标签采用SMIC 0.18μm RF CMOS工艺设计并流片,采样时钟为2MHz,总工作电流少于2μA.     

基于CMOS工艺的太赫兹振荡器

在太赫兹频段,无源器件电容电感的品质因数低、电路的寄生参数以及MOS管的截止频率影响使太赫兹振荡器电路难以实现高功率输出。提出一种300 GHz可调谐振荡器,首先,采用改进的交叉耦合双推(Push-Push)振荡器结构,通过输出功率叠加的方法输出二次谐波300 GHz信号,增加了振荡器的输出功率并突破了MOS管截止频率,并通过增加栅极互连电感增加输出功率。其次,太赫兹振荡器摒弃传统片上可变电容调谐的方式,通过调节MOS管衬底电压改变MOS管的栅极寄生电容实现频率调谐,避免太赫兹频段引入低Q值电容,进一步增加了输出功率。提出的太赫兹振荡器采用台积电40 nm CMOS工艺,基波工作频率为154.5 GHz,输出二次谐波为 309.0 GHz,输出功率可达-3.0 dBm,相位噪声为-79.5 dBc/Hz@1 MHz,功耗为28.6 mW,频率调谐范围为303.5~315.4 GHz。     

低频信号发生器的设计

信号发生器广泛应用于电子工程、通信工程、自动控制、遥测控制、测量仪器、仪表和计算机等技术领域.采用集成运放和分立元件相结合的方式,利用迟滞比较器电路产生方波信号,以及充分利用差分电路进行电路转换,从而设计出一个能变换出三角波、正弦波、方波的简易信号发生器.通过对电路分析,确定了元器件的参数,并利用Multisim软件仿真电路的理想输出结果,克服了设计低频信号发生器电路方面存在的技术难题,使得设计的低频信号发生器结构简单,实现方便.该设计可产生低于10 Hz的各波形输出,并已应用于实验操作.     

Single‐Electron Pass‐Transistor Logic with Multiple Tunnel Junctions and Its Hybrid Circuit with MOSFETs

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single‐electron pass‐transistor logic circuit employing a multiple‐tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single‐electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3‐MTJ inverter circuit is simulated at 15 K with parameters C_g=C_T=C_clk=1 aF, R_T=5 MΩ, V_clk=40 mV, and V_in=20 mV. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ‐SETD logic is successfully translated to the voltage state logic.     

A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.     

Physical random number generator based on MOS structure after soft breakdown

We present a novel physical random number generator (RNG) that uses a metal-oxide semiconductor (MOS) capacitor after soft breakdown (SBD) as a random source. It is known that the electrical properties of MOS capacitors after SBD show large fluctuation. When the resistor in an astable multivibrator is replaced with an MOS capacitor after SBD, the multivibrator converts the noise signal into a rectangular wave whose period fluctuates randomly. A 1-bit counter and a flip-flop are used to generate random numbers from the fluctuating rectangular wave. Some high-level tests indicate that the generated random numbers have excellent quality for cryptographic applications. Even though our circuit is small and can be constructed using about 20 complementary-MOS logic gates and several passive devices, high-quality random numbers such as those generated by large physical RNGs can be obtained.     

A quasi-analytical SET model for few electron circuit simulation

A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation     

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.     

一款通过抗辐照设计加固技术实现的抗单粒子锁相环

本文设计了一款抗辐照设计加固的锁相环。通过增加一个由锁定探测电路、两个运放和4个MOS器件组成的电荷补偿电路,该锁相环显著地减小了单粒子瞬态引起失锁后系统的恢复时间。许多传统的加固方法主要是致力于提高电荷泵输出结点对单粒子瞬态的免疫力,本文的加固方法不仅能够降低电荷泵输出结点对单粒子瞬态的敏感性,而且也降低了其他模块对单粒子瞬态的敏感性。本文还提出了一种新的描述锁相环对单粒子顺态敏感性的系统模型,基于该模型比较了传统的和加固的锁相环对单粒子瞬态的免疫能力。通过Sentaurus TCAD 仿真平台模拟了单粒子瞬态引起的电流脉冲,用于电路仿真。基于130 nm CMOS 工艺设计了两个锁相环电路,晶体管级的仿真表明本文提出的抗单粒子加固锁相环的恢复时间比传统的锁相环提高了94.3%,同时,电荷补偿电路没有增加系统参数设计的复杂性。     

Single-electron random-number generator (RNG) for highly secure ubiquitous computing applications

Since the security of all modern cryptographic techniques relies on unpredictable and irreproducible digital keys generated by random-number generators (RNGs), the realization of high-quality RNG is essential for secure communications. In this report, a new RNG, which utilizes single-electron phenomena, is proposed. A room-temperature operating silicon single-electron transistor (SET) having nearby an electron pocket is used as a high-quality, ultra-small RNG. In the proposed RNG, stochastic single-electron capture/emission processes to/from the electron pocket are detected with high sensitivity by the SET, and result in giant random telegraphic signals (GRTS) on the SET current. It is experimentally demonstrated that the single-electron RNG generates extremely high-quality random digital sequences at room temperature, in spite of its simple configuration. Because of its small-size and low-power properties, the single-electron RNG is promising as a key nanoelectronic device for future ubiquitous computing systems with highly secure mobile communication capabilities.     

Compact floating-gate true random number generator

A compact true random number generator (RNG) integrated circuit with adjustable probability is presented. Hot-electron injection is used in a floating-gate MOSFET to program the probability. Measurements show no cross-correlation between adjacent RNG circuits, allowing multiple RNGs to be easily integrated