基于遗传算法的数字电路试生成方法

本文提出了一种基于遗传算法的数字电路测试图形生成方法，首先把被测电路的门细描述转化为易于计算的非线性网络，然后用遗传算法找到网络能量函数的最优解，从而得以被测电路的测试集。     

一种基于神经网络的组合电路测试生成算法

介绍了一种基于神经网络的组合电路测试生成算法。利用Hopfield神经网络模型将组合电路表示成对应的神经网络,通过建立被测电路的约束网络,构造神经网络的能量函数,使组合电路的测试矢量对应神经网络能量函数的最小值点,使得测试生成问题数学化,并使用遗传算法求解能量函数的最小值点得到故障电路的测试矢量。通过在一些标准电路的实验表明,该测试生成算法有效可行。     

可编程逻辑阵列自检电路的设计及其故障检测方法

本文介绍一项实现可编程逻辑阵列(PLA)的自检电路的新计划。该电路简单、实用、易于测试。在自检过程中,这种包括待测电路(CUT)在内的自检电路是通过待测电路的输出信号反馈到它的输入端而构成。通过研究自检电路的特性,我们能够借助于待测电路及用于检测目的的附加硬件而检测出故障或确定出故障位置。我们将这种自检手段应用于易于测试的、已知功能的 PLA 中,就可以做成一种不依赖功能的测试装置。因此,只要给那些能完成各种功能的 PLA 添加若干个硬件,就能得到一种很简单的、与功能无关的故障自检方法,而不需要用外部电路。例如,用于存储测试图形和(或)压缩输出图形的存储器。本文就自检 PLA 作了详述。     

基于分布估计算法的组合电路测试生成

基于遗传算法生成的测试矢量集的故障覆盖率要低于确定性方法．本文分析指出造成这种现象的一个可能原因在于，组合电路测试生成过程中存在高阶、长距离模式，从而导致遗传算法容易陷人局部极值或早熟收敛．为此，本文首次提出使用分布估计算法生成测试矢量．该方法使用联合概率分布捕捉电路主输人之间的关联性。从而避免了高阶、长距离模式对算法的影响，缓解了算法早熟收敛问题．针对ISCAS-85国际标准组合电路集的实验结果表明，该方法能够获得较高的故障覆盖率．     

电路测试生成的神经网络方法研究

本文研究将人工神经网络用于组合电路测试产生的一般模型，分析影响这一方法，效率的因素，提出了用于降低被测电路对应网络规模的故障压缩，电路分块，多级蕴涵等策略，采用改进的梯度算法加建了网络能量函数极小值的搜索。介绍了基于这些策略开发的一个测试生成系统的结构。实验结果说明了提出方法的有效性。     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

基于遗传算法的自适应测试生成

文章介绍了一种基于遗传算法的自适应测试生成方法，首先讨论了用遗传算法进行测试生成时构造评价函数的一些方法，然后应用组合电路的Hopfield神经网络模型，提出了基于遗传算法的自适应测试生成算法，该方法不同于传统的方法，它不需要故障传播传播、回退等过程，实验结果表明了本算法的可行性。     

易测电路的构成及其测试生成算法

本文提出一种将任意组合电路转变为易测电路的方法和易测电路的测试生成算法。对电路中所有引线的单固定故障都能产生测试向量。测试生成所需的计算量的上限是2(n_1+4n_2)~2。     

能量极小化的一种启发式遗传算法

Ｃｈａｋｒａｄｈａｒ ｅｔ．ａｌ（１９８８，１９９０）将组合电路表示为Ｈｏｐｆｉｅｌｄ神经网络，将测试生成问题转化为一个组合优化总理２。本文在传统遗传算法的基础上，结合电路的拓扑信息，提出了一咱用于组合电路神经网络模型能量极小化的启发式遗传算法。     

基于VHDL语言的数字电路测试码自动生成

本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。在VHDL语言描述组合数字电路的基础上,建一VHDL语言的编译器,并输入为描述被测电路的VHDL语言,输出结果为描述被测电路功能的一系列逻辑表达式。针对这些逻辑表达式,本文详细地介绍了一种能直接产生电路测试码的算法。     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

模拟电路故障诊断的PSpice与Matlab仿真分析研究

根据模拟电路故障诊断中的测前模拟诊断SBT法,本文采用PSpice对待测电路CUT故障进行模拟仿真,通过小波包分析和信息熵方法提取故障电路输出信号的特征向量,利用Matlab设计的神经网络算法构建故障分类器并对电路故障进行识别与诊断。仿真实验结果表明将PSpice与Matlab相结合的诊断方法能够有效地诊断模拟电路故障,为模拟电路故障诊断的教学和科研提供参考。     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

Analog Circuits Fault Detection Using Cross-Entropy Approach

This paper presents a novel method that can detect component faults in analog circuits. Because the probability density function (PDF) of output voltage (current) is sensitive to the components of the circuit, the cross-entropy between the good circuit and the bad circuit is employed to detect component faults in analog circuits based on the autoregressive (AR) model. In the proposed approach, the value of each component of the circuit undertest (CUT) is varied within its tolerance limit using Monte Carlo simulation. The minimal and maximal bounds of the cross-entropy are found for fault-free circuit. While testing, the cross-entropy is obtained. If cross-entropy lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is demonstrated via the second order Sallenkey bandpass filter circuit and continuous-time low pass state-variable filter circuit.     

Soft Fault Diagnosis in Analog Circuits Based on Bispectral Models

Aiming at the problem to locate soft faults in analog circuits, a new approach based on bispectral models is proposed. First, the Volterra kernels of the circuit under test (CUT) are calculated. Then, the Volterra kernels are used to construct bispectral models. By comparison with the fault features of the constructed models, soft faults of linear and weak nonlinear components in the analog circuit are identified and the faults are located. Simulations and experiments show the effectiveness of the proposed method in analog circuits.,     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.