AVC/H.264整数离散余弦变换及反变换的结构设计

根据AVC/H.264标准中提出的整数离散余弦变换(DCT)及其反变换(iDCT)算法,旨在给出一种能够同时实现4×4,8×8 DCT/IdCT和Hadamard变换的设计方法.设计中充分利用DCT和iDCT的相似性和算法对称性,用高度并行结构来加快处理速度.采用一维DCT/iDCT单元复用的方式实现二维DCT/iDCT运算,同时提出实现设计的全定制实现方法,对全定制实现此设计进行初步布局规划.     

AVCHD高清摄像机及其视频格式

MPEG-4 AVC/H.264是目前最新的国际视频压缩标准,已被确定为下一代影视光盘(Blue-rayDisc)和HD DVD(高清DVD)的视频编码标准之一。简要介绍AVCHD高清摄像机的主要性能指标,重点对MPEG-4 AVC/H.264的特点和应用进行了分析。     

H．264／AVC中量化的Verilog实现

视频压缩技术取得了日新月异的发展.运动图像专家组和视频编码专家组给出一种更好的视频压缩标准,确定为MPEG-4标准的第十部分,即H.264/AVC.H.264/AVC作为新一代视频压缩标准,具有超高压缩率.详细分析了H.264中量化算法,并用Verilog硬件描述语言编程实现量化功能,利用Modelsim进行仿真,得到正确的结果.分析了量化模块所消耗的硬件资源,提出用FPGA实现H.264量化的算法,使H.264能够用硬件的方法实现.     

H．264／AVC中的整数变换与DCT变换的比较

数字视频技术在通信和广播领域获得了日益广泛的应用,视频信息和多媒体信息在网络中的处理和传输成为当前我国信息化中的热点技术。运动图像专家组和视频编码专家组给出一种更好的标准,确定为MPEG-4标准的第十部分,即H.264/AVC。简述H.264的研究意义及DCT的原理。为了减少运算量,分析H.264中如何对宏块的整数变换,详述H.264的编码变换的方法,给出整数变换方法与传统的DCT的区别和联系,并给出H.264的整数变换方法的快速算法即蝶形算法,这与传统的DCT变换是不同的。     

H.264熵解码器CAVLC的硬件设计

H.264/AVC是ITU-T和MPEG组织共同推出的最新一代视频压缩标准,其压缩效率较H.263和MPEG-4 simple profile有显著提高.     

H.264/AVC中变换量化模块的可重构设计

基于H.264/AVC视频编码标准,完成编码模块中的整数OCT/Q模块可重构IP核的优化设计.在硬件开销改变不大的情况下,利用可重构理论,提炼出其核心部件即可重构处理元,在同种电路结构上实现变换量比(DCT/Q)和反变换反量比(IDCT/IQ)的功能,满足高清视频实时编解码要求.     

一种新的视频编解码H.264/AVC

H.264/AVC(先进的视频编码)已经被作为下一代高清晰度DVD的标准,这种编解码技术的普及正日益增长。最新报告显示,业内相当多的公司声称已制定出采用H.264/AVC标准的计划并推出了供展示的产品样品。 目前正在将由ITU-T与MPEG(移动图象专家组)联合开发的此项视频压缩标准(全称为H.264或MPEG-4pt.10/AVC)应用到产品中的公司包括:美国苹果公司、日本索尼公司、英国电信、法国电信、英特尔公司、摩托罗拉、诺基亚、     

H.264/AVC在3G移动通信中的应用

H.264/AVC是目前最新,也是性能最优异的国际视频压缩编码标准。在相同的视频质量下,H.264/AVC可以比MPEG-4(SP)节省大约一半的带宽,同时还具有更好的网络适应性和传输健壮性,在3G移动通信系统带宽资源紧张、通信环境恶劣的情况下,H.264/AVC应该是目前最合适的选择。从压缩效率、网络适应性和健壮性3个方面分析了H.264/AVC的新技术,并讨论了它们在3G移动通信中的应用。     

一种高效可编程H.264/AVC比特流解析结构设计

在分析H.264/AVC比特流结构和位级处理需求的基础上,本文提出了一种用于H.264/AVC带有指令集的可编程比特流解析结构.由于它是基于硬件的结构,与通用RISC结构相比效率更高.实验表明,在以4 Mbit/s的比特率传输H.264/AVC主类720×576@25 f/s时,整个比特流解析仅需要14.3 MI/s.它还能灵活地应用到MPEG-2或其他不同的视频标准比特流解析中.     

用于H.264编解码的面向HDTV应用的动态可重构多变换VLSI结构

提出了一种新的支持MPEG-4 AVC/H.264标准4×4整数变换的动态可重构结构.首先,针对4×4正反变换分别推导了两个新的二维直接信号流图.进而设计了一个面向HDTV应用的动态可重构多变换结构.该结构无需转置寄存器且计算单元仅需16个加法器(减法器).采用0.18μm CMOS工艺实现了该电路结构.结果表明,最高...     

General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

The latest international video-coding standard H.264/AVC significantly achieves better coding performance compared to prior video coding standards such as MPEG-2 and H.263, which have been widely used in today’s digital video applications. To provide the interoperability between different coding standards, this paper proposes an efficient architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC intra frame transcoding, using the original information such as discrete cosine transform (DCT) coefficients and coded mode type. Low-frequency components of DCT coefficients and a novel rate distortion cost function are used to select a set of candidate modes for rate distortion optimization (RDO) decision. For H.263 and H.264/AVC, a mode refinement scheme is utilized to eliminate unlikely modes before RDO mode decision, based on coded mode information. The experimental results, conducted on JM12.2 with fast C8MB mode decision, reveal that average 58%, 59% and 60% of computation (re-encoding) time can be saved for MPEG-2, H.263, H.264/AVC to H.264/AVC intra frame transcodings respectively, while preserving good coding performance when compared with complex cascaded pixel domain transcoding (CCPDT); or average 88% (a speed up factor of 8) when compared with CCPDT without considering fast C8MB. The proposed algorithm for H.264/AVC homogeneous transcoding is also compared to the simple cascaded pixel domain transcoding (with original mode reuse). The results of this comparison indicate that the proposed algorithm significantly outperforms the mode reuse algorithm in coding performance, with only slightly higher computation.     

新一代视频编码标准HEVC变换方法的研究

高性能视频编码( HEVC)将成为国际最新的视频编解码标准.该标准主要针对目前应用日益广泛的高清甚至超高清视频而开发,其编码的性能目标是在保持原来H.264/AVC的视频质量的同时,将比特率再降低一半.与原有标准一样,HEVC对帧内或帧间的残差信号进行正交变换以集中能量至矩阵左上角,然而H.264/AVC标准中的传统DCT方法对于高清视频的处理已不能有较好效果.讨论研究目前针对HEVC正交变换提出的变换方法,包括基于模式的方向变换MDDT、自适应离散余弦/正弦变换(DCT/DST)、旋转变换(ROT)、IDCT修剪和变换跳过模式(TSM)等方法.实验结果显示了上述几种方法在比特率降低、编码时间缩短、软硬件实现复杂度降低和客观视频质量等方面的改进.最后,提出了对HEVC正交变换的进一步研究方向.     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

一种新的基于VLIW的IDCT和运动补偿算法

本文使用矩阵形式在超长指令字(VLIW)的观点下将几种经典算法与已有的适合于VLIW的算法进行了比较.然后利用VLIW结构的特性,提出了一种快速IDCT算法.与现有算法相比,新算法进一步减少了所需的指令周期.并利用VLIW结构的寄存器特性,将视频编解码过程中的运动补偿(预测)和IDCT(DCT)组合,使运动补偿所需时间降低为原来的约50%,这种思想能应用于MPEG1/2/4,H.263和H.264.     

Video coding with H.264/AVC: tools, performance, and complexity

H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.     

Video transcoding from H.264/AVC to MPEG-2 with reduced computational complexity

This paper addresses video transcoding from H.264/AVC into MPEG-2 with reduced complexity and high rate-distortion efficiency. While the overall concept is based on a cascaded decoder–encoder, the novel adaptation methods developed in this work have the advantage of providing very good performance in H.264/AVC to MPEG-2 transcoding. The proposed approach exploits the similarities between the coding tools used in both standards, with the objective of obtaining a computationally efficient transcoder without penalising the signal quality. Fast and efficient methods are devised for conversion of macroblock coding modes and translation of motion information in order to compute the MPEG-2 coding format with a reduced number of operations, by reusing the corresponding data embedded in the incoming H.264/AVC coded stream. In comparison with a cascaded decoder–encoder, the fast transcoder achieves computational complexity savings up to 60% with slightly better peak signal-to-noise ratio (PSNR) at the same bitrate.     

Hardware solution for implementing the entire inverse IDCTs in HEVC decoder

Video compression performance of High Efficiency Video Coding (HEVC) is about twice of H.264/AVC video compression standard. The improvement in coding efficiency in HEVC is achieved by considerable increase in the computational load compared to H.264/AVC which is substantially very computational intensive. One of the units in HEVC which has changed considerably compared to H.264/AVC is Integer Discrete Cosine Transform (IDCT) unit. IDCT in HEVC standard includes 32 × 32, 16 × 16, 8 × 8 and 4 × 4 transforms. In this paper, a hardware solution for implementing the entire inverse IDCTs in HEVC decoder is proposed. The proposed hardware has a resource-sharing pipelined architecture. As a result, the hardware resources and computation time for implementing inverse IDCTs in HEVC decoder are reduced. Synthesis results by using NanGate OpenPDK 45 nm library indicate that the proposed hardware can achieve 222 MHz clock rate and can achieve real-time decoding of 4096 × 3072 video sequences with 70 fps.     

A DCT/DST-based error propagation-free data hiding algorithm for HEVC intra-coded frames

Currently, two error propagation-free discrete cosine transform (DCT)-based data hiding algorithms, one by Ma et al. and the other by Lin et al., were presented for H.264/AVC intra-coded frames. However, the state-of-the-art video codec, high efficiency video coding (HEVC), adopts both integer DCT and discrete sine transform (DST) such that the previous DCT-based algorithms cannot fully utilize available capacity for data hiding in HEVC. This paper presents the first DCT/DST-based data hiding algorithm for HEVC intra-coded frames where the block DCT and DST coefficient characteristics are investigated to locate the transformed coefficients that can be perturbed without propagating errors to neighboring blocks. Experimental results confirm the merits of the proposed algorithm in providing the intra-frame error propagation-free advantage, the quality improvement for marked images, the compression power inherited from HEVC, and the superiority of embedding capacity for low bitrate coding when compared with the previous two algorithms for H.264/AVC.