Linearization of direct FM frequency modulators

Voltage controlled crystal oscillator (VCXO) frequency modulators have found increasing use in recent years in portable frequency modulation (FM) equipment as an alternative to a standard crystal oscillator followed by a phase modulator. The advantages of using a direct FM VCXO over an indirect FM phase modulator are considered. A model for the crystal and frequency control element will be developed and basic circuit design considerations will be presented. Conditions necessary to minimize audio distortion generated by the VCXO modulator will be dealt with in detail.     

基于多项式拟合频率重构的物理不可克隆函数优化

近年来硬件安全不断受到挑战,具有不可预测性、随机性等特性的环形振荡器物理不可克隆函数(Ring Oscillator Physical Unclonable Function,RO PUF)可作为硬件安全重要的加密密钥方式,但通常原始RO PUF不满足加密密钥对随机性的要求。因此,提出了基于多项式拟合频率重构的PUF优化方法。首先,实现RO电路的硬宏设计并在现场可编程门阵列(Field Programmable Gate Array,FPGA)上进行实例化,从而获得RO阵列的频率数据;其次,针对原始响应的随机性较差的情况,通过统计分析其分布特征,利用多项式拟合法优化重构RO阵列频率;最后,采用熵密度值评估RO PUF响应的随机性。选用型号为Xilinx Artix 7103的FPGA板进行实验测试评估,结果表明所提方法不仅比原始RO PUF响应的随机性强,而且与随机补丁混合法(Random Patch Mixer,RPM)和基于回归的熵蒸馏法相比也具备更好的随机性。     

High frequency dividing synchronous oscillator using modified emitter couple logic inverters

A synchronous oscillator using a high speed low-voltage emitter coupled logic (ECL) inverter has been reported. Using the positive feedback the locking range increases, compared to the oscillator without any positive feedback. A maximum improvement (increase) of percentage locking range of around 105% was obtained from circuit simulation as well as from practical circuit, using discrete components. Because the locking range is maximum at double the output frequency of the oscillator, this oscillator can be used as a high frequency divider circuit. The circuit requires a supply voltage of 2.1 V.     

A digital signal processing type frequency locked loop for frequency shift keying demodulation

In this paper, we propose a digital signal processing type frequency locked loop (DSP-FLL) using a frequency difference detector (FDD). Since the DSP-FLL is controlled by the frequency, the pole of the voltage controlled oscillator vanishes in the baseband equivalent circuit. Therefore, the transfer function becomes first order and a ringing does not occur. Furthermore, it can be understood from the detection property of the FDD that a cycle slip does not occur and the DSP-FLL can pull in the frequency step input up to half of the sampling frequency.     

10 GHz LC-tuned VCO with coarse and fine frequency control

The authors present a monolithic 10 GHz voltage-controlled oscillator (VCO) using an LC resonant circuit for tuning. The basic approach for designing this fully differential VCO will be described, followed by practical modelling considerations, and an explanation of experimental results. Two methods of tuning the resonant frequency will also be addressed with respect to their impact on circuit performance     

A new fraction phase based low energy frequency calibration architecture along with an ultra low power VCO design

This paper presents the design and analysis of the architecture of a fraction phase based frequency calibration unit where the number of delay cells (that sense the fraction phase) have been reduced to zero. As no pre-calibration of the delay values are required, it becomes immune to process-voltage-temperature variation. Simulation results for frequency convergence have been provided for different target frequencies of an LC oscillator and for an accuracy of 400 ppm. The paper next presents the design and analysis of a voltage controlled oscillator in the form of an astable multivibrator that is similar to a single stage ring oscillator. A novel resistive tuning technique that occupies small chip area and provides less process variation and more matching has been proposed. Also, it has been shown that although the oscillator’s phase noise is worse than LC oscillator, the frequency convergence probability (when using the frequency calibration unit with 4 delay cells, due to the high jitter values) does not degrade significantly with the same calibration unit specifications. Hence successful integration of the oscillator with the calibration unit is possible with the advantage of having fully on-chip design with lower power consumption than that of LC oscillators. The oscillator and the calibration circuit have been designed in UMC 180 nm technology that together consume a current of 320µA (in simulation) from 1.6 V power supply. The designs have been targeted for implant telemetry in the 402–405 MHz band having the requirement of ultra low power consumption.

     

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying?±?1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

     

A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibratedΣ-Δ frequency synthesizer

This paper describes a new sigma-delta (Σ-Δ) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), Σ-Δ modulator, and automatic calibration circuit, has been implemented in a 0.6-μm BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

A low frequency sine wave oscillator†

A now variable frequency oscillatory system is described. For certain system conditions the circuit produces a sine wave oscillation whose Frequency is varied over n wide range from ft very low to a high value simply by varying the gain of an amplifier rather than by changing the circuit time constant and accordingly no ganged condensers are used. Another important feature of the circuit is that the generation of a very low frequency oscillation is possible without incorporating a large value of the KC product. The oscillator utilizes an amplitude stabilizer operating on the controlled linear resistance of the initial region of the characteristic of a junction KET. The frequency relation is derived and the results are compared with experiment and found in agreement.     

A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

A frequency-synthesis technique which extracts the Nth harmonic from an N-stage oscillator is presented. This technique enables significant power savings in the prescaler of a frequency synthesizer. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled single-ended three-stage ring oscillators has been fabricated in 0.24-/spl mu/m CMOS, designed to work in the 902-928-MHz ISM band (U.S. and Canada). It provides two outputs: one at the normal operating frequency of the oscillator and the other at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.     

Switching delay of a nonlatching Josephson gate evaluated from ringoscillator operation

The authors present the experimental results for the switching delay of a dc-biased nonlatching Josephson gate (a coupled-superconducting quantum interference device gate). The measurement is executed by the use of a ring oscillator (RO) method. A frequency-to-voltage converter is used to evaluate the oscillation frequency of the RO. The circuit is designed and fabricated using a 2.5-kA/cm² Nb/AlO_x/Nb Josephson junction technology. The results show the minimum switching delay of 18 ps     

X波段GaAs单片压控振荡器

本文报告了X波段GaAs单片压控振荡器的设计和制作,电路设计采用小信号CAD分析程序,能准确地预计振荡频率,同时利用特殊工艺途径提高了变容管Q值.单片电路调谐范围是9.3～11.6GHz,输出功率大于10dBm.     

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

CMOS realization of single-resistance-controlled and variable frequency dual-mode sinusoidal oscillators employing a single DVCCTA with all-grounded passive components

In this paper, two new designs are proposed for sinusoidal oscillators based on a single differential voltage current conveyor transconductance amplifier (DVCCTA). Each of the proposed circuits comprises a DVCCTA combined with passive components that simultaneously provides both voltage and current outputs. The first circuit is a DVCCTA-based single-resistance-controlled oscillator (SRCO) that provides independent control of the oscillation condition and oscillation frequency by using distinct circuit parameters. The second circuit is a DVCCTA-based variable frequency oscillator (VFO) that can provide independent control of the oscillation frequency by adjusting the bias current of the DVCCTA. In this paper, the DVCCTA and relevant formulations of the proposed oscillator circuits are first introduced, followed by the non-ideal effects, sensitivity analyses, frequency stability discussions, and design considerations. After using the 0.35-μm CMOS technology of the Taiwan Semiconductor Manufacturing Company (TSMC), the HSPICE simulation results confirmed the feasibility of the proposed oscillator circuits.     

高线性度低频压控振荡器的设计

文章提出了一种由积分器、比较器以及控制电路和逻辑电路构成的压控振荡器，并对其低频线性度、结构特性等性能进行了较为深入的分析。利用xFAB xdm10工艺模型在spectre上的模拟结果表明．由于采取内部补偿措施，可在相当低的频段内（20KHz～1．5MHz）将其线性误差从1．68％降低到了0．4％；同时，这种经过改进的压控振荡器很好地解决了低频噪声和低频线性度的问题，消除了放电误差，适用于精密的工业控制场合。     

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

D类音频功放中电流控制振荡器的设计

基于N阱0．5μmDPTM CMOS工艺,完成了D类音频功放中电流控制振荡器的设计。首先分析了电流控制振荡器的工作原理,然后着重介绍了振荡器的设计。仿真结果表明,5V电源电压下振荡器的频率为250kHz,温度在-40-120℃,电源电压在3-5V范围内,频率随温度和电源电压的改变很小,仅为4％。该电路应用于某款D类音频功放芯片。     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.