提高晶圆扫描效率的方法研究

从测试晶圆上未划切的手机摄像头芯片引出一个问题:如何快速确定晶圆的有效测试范围,提出了"全片扫描"和"边缘扫描"两种方法,阐述实现原理后,分析各自的优缺点,利用实验数据进行效率对比,发现"边缘扫描"效率更高。     

密码芯片安全扫描结构及安全扫描方法研究

随着物联网、云计算等技术的发展,网络信息安全更加受到关注。密码芯片是信息安全的基础,不能保障密码芯片的自身密钥安全,根本无法保障信息安全。在各类数字芯片中,扫描测试结构应用广泛。扫描测试结构是可测性设计结构,测试代价较低,测试覆盖率充足,对电子系统的可靠性有重要的价值。扫描测试结构虽然增加了密码芯片的可测性,但出现使用不当,可能作为旁路攻击路径,泄露密码芯片的密钥信息。文章对此提出前馈异或安全扫描结构,扫描结构中引入异或安全扫描寄存器,变换测试图形的输入/输出,加密测试图形的硬件,分析其测试图形生成算法。     

考虑测试功耗的扫描链划分新方法

提出考虑测试功耗的扫描链划分新方法.首先为基于扫描设计电路的峰值测试功耗和平均功耗建模,得出测试功耗主要由内部节点的翻转引起的结论,因此考虑多条扫描链情况,从输入测试集中寻找相容测试单元,利用扫描单元的兼容性,并考虑布局信息,将其分配到不同的扫描链中共享测试输入向量,多扫描链的划分应用图论方法.在ISCAS89平台上的实验结果表明,有效降低了峰值测试功耗和平均测试功耗.     

部分扫描可测性设计中扫描链的构造

提出了时序电路的部分扫描法可测性设计中扫描链的构造方法，包括扫描链的选取、扫描链的排序、多链扫描设计三部分内容。采用组合等效电路的方法求测试向量，并用实例进行了验证，模拟结果表明，选取２０％￣４０％的触发器至扫描链，用较少的测试向量，可达到很理想的故障覆盖率，测试时间依赖于触发器在扫描链中的顺序以及扫描链的个数。     

一种先进的有线电视扫描测试系统

本文介绍了有线电视系统测试中，扫描测试的重要性及必要性，重点介绍了隐形扫描测试方法的先进性及如何应用隐形扫描系统方便地完成了扫描测试，并指出了随着有线电视事业的发展，越来越多的人将认识到扫描测试是不可少的重要测试之一。     

JTAG测试中扫描链的配置问题研究

分析了常见扫描链路配置中面临的问题,提出了一种扫描链配置方案。结合工程测试中出现的实际问题,给出了有关扫描链路配置的一些建议和注意事项。     

基于边界扫描技术的板级测试分析

随着支持IEEE1149.1标准的边界扫描芯片的广泛应用,传统的电路板测试方法如使用万用表、示波器"探针",已不能满足板级测试的需求,相反一种基于板级测试的边界扫描技术得到了迅速发展。对边界扫描测试技术的原理进行了剖析,根据边界扫描测试系统的使用规则对板级测试方法进行了分析、提出了整体测试流程,最后在通用测试的基础上进行了二次开发,提出了提高电路板测试覆盖率的方法。     

混合信号边界扫描测试系统的设计与实现

分析了混合信号边界扫描测试的工作机制对测试系统的功能需求,实现了符合IEEE1149.4标准的混合信号边界扫描测试系统。仿真和测试实践表明,该测试系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,结构简单、携带方便、工作可靠。     

边界扫描板级链路测试性设计方法研究

边界扫描技术是一种新型的VLSI电路测试及可测性设计方法.但是在扫描链路的设计中如何将不同厂家、不同型号、不同工作电压的BS器件实现JTAG互连,如何将边界扫描测试、在线编程和在线仿真结合起来一直是一个亟待解决的问题.为解决上述问题,本文提出了两种基于边界扫描技术的板级动态链路设计方法.这种可测性设计技术不仅能完成边界扫描测试,还能完成在线编程或在线仿真等功能,具有很好的测试设计灵活性.     

非扫频扫描测试在HFC网络正向通道上的应用

本文提出了在有线电视HFC网络正向通道上进行非扫频扫描测试的观点。指出了没有使用扫频发射机也能获取扫描信息。介绍了非扫频扫描测试原理和在有线电视HFC网络上应用的方法。     

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.     

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains     

基于OLED微显示器的原子扫描控制器设计

头戴式虚拟现实(Virtual Reality,VR)显示的持续升温推动微显示器不断向高分辨率、高刷新率的方向发展,然而微显示器有限的带宽难以承载虚拟世界下的海量图像数据,为了减少微显示器系统扫描成像过程中的时间冗余,提高数据传输效率和图像线性度,建立了一种伪随机扫描顺序的原子扫描模型。传统的微显示器是从第一个像素到最后一个像素连续顺序扫描的,原子扫描采用分子空间按位的扫描方法,将整个显示屏幕分成若干子空间,扫描时可以任意切换子空间。根据原子扫描模型设计了微显示器的原子扫描控制器,通过分辨率为1.6k×3×1.6k硅基OLED微显示器的验证,扫描达到了100%的传输效率和93.8%的线性度,相比于传统的十二子场扫描,时钟频率降低了约3.3倍。证明了原子扫描控制器的可行性,适用于超高清、高分辨率、海量数据的图像显示。     

Test data compression technique for embedded cores using virtual scan chains

This paper presents a design-for-test (DFT) technique to implement a "virtual scan chain" in a core that looks (to the system integrator) like it is shorter than the real scan chain inside the core. A core with a "virtual scan chain" is fully compatible with a core with a regular scan chain in terms of both the external test interface and tester program. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a regular scan chain. For the system integrator, testing a core with a virtual scan chain is identical to testing a core with a regular scan chain (no special modes, control signals, or timing sequences are needed). The only difference is that the virtual scan chain is much shorter so the size of the scan vectors and output response is smaller resulting in less test data as well as less test time (fewer scan shift cycles). The process of mapping the virtual scan vectors to real scan vectors is handled inside the core and is completely transparent to the system integrator.     

A Low Power Pseudo-Random BIST Technique

Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.     

Physical‐Aware Approaches for Speeding Up Scan Shift Operations in SoCs

System‐on‐chip (SoC) designs have a number of flip‐flops; the more flip‐flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical‐aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout‐aware flip‐flop insertion and scan shift operation–aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state‐of‐the‐art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.     

全扫描设计中多扫描链的构造

本文在交迭测试体系 的基础上提出了一种多扫描链的区间构造法,对于确定的测试向量集能够显著地减少测试应用时间.该构造方法根据规定的扫描链数,通过求解线性规划问题的方法确定扫描寄存器在扫描链上的优化的分布区间,从而构造多扫描链,最后根据对多扫描链进行连线复杂度的定性分析,求得连线复杂度最低的多扫描链的最优构造.     

Decentralized BIST Methodology for System Level Interconnects

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.     

Why current secure scan designs fail and how to fix them?

Scan design has become another side channel of leaking confidential information inside cryptographic chips. Methods based on obfuscating scan chain order have been proposed as countermeasures for such scan-based attacks. In this paper, we first analyze the existing secure scan designs from the angle that whether they need a complete chain state or rely on any specific scan chain order. We show that all existing attacks do not rely on specific scan chain order and therefore any secure scan design with obfuscated scan chain order cannot provide sufficient security. We then propose a new approach which clears the states of all sensitive scan cells whenever the circuit under test is switched to test mode. It will also block the access to cipher key throughout the entire testing process. Our experimental results show that the proposed scan design can effectively insulate all the information related to cipher key from the scan chain with little design overhead, thus it can successfully defend all the existing scan-based attacks.     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.