基于单一PMOS差分对的轨到轨输入运算放大器设计

基于国内某CMOS工艺设计了一种单一PMOS差分对的轨到轨输入、恒跨导CMOS运算放大器。输入级电路采用折叠共源共栅结构,通过体效应动态调节输入管的阈值电压扩展共模输入范围到正负电源轨,恒定共模输入范围内的跨导,自级联电流镜有源负载将差分输入转换为单端输出;输出级电路采用AB类结构实现轨到轨输出,线性跨导环确定输出管的静态偏置电流。在5 V电源电压,2.5 V共模电压,1 MΩ负载条件下,经Spectre仿真验证,该运算放大器开环增益为119 dB,相位裕度为58°,共模输入范围为0.0027～4.995 V,共模范围内跨导变化小于3%,实现了轨到轨输入共模范围内的跨导恒定。     

一种低电压恒定跨导轨到轨运算放大器的设计

设计了一种低电压恒定跨导的轨到轨运算放大器,作为误差放大器用在BUCK型DC-DC上实现对输出电压的调节。该运算放大器采用两级结构,输入级采用互补差分对的结构,实现了轨到轨电压的输入,并且利用2倍电流镜技术实现了跨导的恒定;输出级采用AB类放大器的结构,提高了输出电压摆幅和效率,实现了轨到轨电压的输出。该电路基于CSMC 0.25μm EN BCDMOS工艺进行设计,仿真结果表明:电源电压为2.8 V时,在输出端负载电容为160 pF、负载电阻为10 kΩ的情况下,增益为124 dB,单位增益带宽积为5.76 MHz,相位裕度为59.9℃,输入跨导为5.2 mΩ~(-1),共模抑制比为123 dB,输入共模信号范围为0～2.8V,输出电压摆幅为0～2.8 V。     

一种0.8V衬底驱动轨对轨运算放大器设计

采用衬底驱动技术设计低压低功耗轨对轨运算放大器。输入级采用衬底驱动MOSFET,有效避开阈值电压限制,将电源电压降至0.8V,实现低压下轨对轨共模输入范围。增加衬底驱动冗余差分对及反折式共源共栅求和电路实现恒定跨导控制,消除共模电压对输入级跨导的影响,输出采用前馈式AB类输出级,以提高动态输出电压范围。基于标准0.18μmCMOS工艺仿真运放,测得输出范围0.4～782.5mV,功耗48.8μW,电源抑制比58dB,CMRR65dB,直流开环增益63.8dB,单位增益带宽2.4MHz,相位裕度68°。版图设计采用双阱交叉空铅技术,面积为97.8μm×127.6μm。     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

恒跨导轨对轨CMOS运算放大器的设计

为了提高运算放大器对电源电压的利用率,基于GSMC 0.18 μm CMOS工艺模型,设计了一种高增益恒跨导轨对轨CMOS运算放大器。该运算放大器的输入级采用了互补差分对,并通过3倍电流镜法保证输入级总跨导在整个共模输入范围内恒定;为了获得较大的增益和输出摆幅,中间级采用了折叠式共源共栅结构;输出级采用了AB类输出控制电路,使输出摆幅基本实现了轨对轨。在3.3 V供电电压以及1.6 V输入电压下,该放大器的直流增益为126 dB,单位增益带宽为50 MHz,相位裕度为65°。电路结构简单,易于调试,可大大缩减设计周期和成本。     

一种恒跨导高增益轨到轨运算放大器

基于TSMC 0.18 μm CMOS工艺,设计了一种新颖的恒跨导高增益轨到轨运算放大器。输入级仅由NMOS管差分对构成,采用电平移位及两路复用选择器控制技术,在轨到轨共模输入范围内实现了输入级恒跨导。中间级采用折叠式共源共栅放大器结构,运算放大器能获得高增益。输出级采用前馈型AB类推挽放大器,实现轨到轨全摆幅输出。利用密勒补偿技术进行频率补偿,运算放大器工作稳定。仿真结果表明,在1.8 V电源电压下,该运算放大器的直流开环增益为129.3 dB,单位增益带宽为7.22 MHz,相位裕度为60.1°,整个轨到轨共模输入范围内跨导的变化率为1.44%。     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器

设计了一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器.输入级采用PMOS差分对结构,通过电荷泵产生高于电源电压的输入级内电源,使运放在轨到轨输入范围能正常工作并保持输入跨导恒定.电荷泵电路所需的时钟信号通过内部振荡器电路产生,再通过电压自举电路和时序电路产生所需电平的非交叠开关控制信号,最后利用时间交织结构输出连续稳定的高压内电源.在电荷泵实现中还采用了辅助开关结合跟随运放的结构降低了主开关在切换时的毛刺.该运放在折叠式共源共栅结构中使用增益自举结构提高了总体增益,输出级采用class AB类输出结构实现轨到轨输出.该运算放大器基于0.5μm CMOS工艺完成电路与版图设计,仿真结果表明,在5 V电源电压下,直流增益为150.76 dB,单位增益带宽为53.407 MHz,相位裕度为96.1°,输入级跨导在轨到轨输入共模范围内的变化率为0.001 25%.     

一种宽带恒定跨导轨对轨运算放大器的设计

介绍了一种具有轨对轨输入功能的CMOS输入级电路。该电路克服了一般运算放大器只能工作在一定共模输入范围的输入级的缺陷，在各种共模输入电平下有着几乎恒定的跨导，使频率补偿更容易实现，且由于其工作原理与MOS晶体管的C—V解析关系无关，对制造工艺依赖性小，适用于深亚微米工艺。在此基础上，设计出了一种宽带的运算放大器，该运算放大器具有轨对轨输入、输出能力，可以作为常用模拟电路的基本单元模块。它没有严格的共模输入限制，跨导和整体性能稳定，适于为更大规模的数字／模拟混合信号系统提供行为级模型。     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

A high bandwidth constant gm and slew-rate rail-to-railCMOS input circuit and its application to analog cells for low voltageVLSI systems

A new rail-to-rail CMOS input architecture is presented that delivers behavior nearly independent of the common-mode level in terms of both transconductance and slewing characteristics. Feedforward is used to achieve high common-mode bandwidth, and operation does not rely on analytic square law characteristics, making the technique applicable to deep submicron technologies. From the basis of a transconductor design, an asynchronous comparator and a video bandwidth op amp are also developed, providing a family of general purpose analog circuit functions which may be used in high (and low) bandwidth mixed-signal systems. Benefits for the system designer are that the need for rigorous control of common-mode levels is avoided and input signal swings right across the power supply range can be easily handled. A further benefit is that having very consistent performance, the circuits can be easily described in VHDL (or other behavioral language) to allow simulation of large mixed-signal systems. The circuits presented may be easily adapted for a range of requirements. Results are presented for representative transconductor, op amp, and comparator designs fabricated in a 0.5 μm 3.3 V digital CMOS process     

A rail-to-rail, constant gain, buffered op-amp for real time videoapplications

Inspired by Hogervorst et al's current switch idea, a buffered output stage operational amplifier was designed, which has high frequency, high dc gain, and rail-to-rail constant transconductance (G _m). This operational amplifier is the output stage of an analog/digital system which implements a Gabor convolution for real-time dynamic image processing and it is designed to interface the external analog-to-digital converter (ADC) with a very heavy load. The op amp was fabricated by the MOSIS service in a 2-μm, n-well CMOS, double polysilicon, double metal technology. The fabricated circuit operates from a single 5 V power supply and dissipates 10 mW. The open loop-gain of the fabricated circuit, A_vol, was measured as 67.2 dB for a 163 Ω∥33 pF load. Other dc and ac characteristics were measured for a 50 Ω∥33 pF load. The unify gain-bandwidth (GBW) was measured to be 11.4 MHz, the rising slew rate (SR+) 20.4 V/μs, the falling slew rate (SR-) 18.8 V/μs, and the offset voltage (V_off) 1 mV. The output swings with an amplitude of 3.24 V between 0.88 V and 4.12 V, which matches the input signal specifications of the ADC. In addition to rail-to-rail output voltage swing, the opamp has a constant G_m over the whole common mode (CM) voltage range     

Constant-Gm rail-to-rail common-mode rangeinput stage with minimum CMRR degradation

The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-μm feature size are given     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion