硅—锗异质合金及其在异质结双极晶体管中的应用

八十年代后期发展起来的硅-锗异质结构材料,得益于成熟的硅技术,正在取得令人鼓舞的成果。采用应变层外延技术,已经获得高质量的Ge_xSi_(1-x)/Si异质膜。这些材料已被应用于各种半导体器件的研究之中。异质结双极晶体管是硅-锗异质结构材料的一个典型应用领域。近期研究结果显示出硅-锗异质结双极晶体管(HBT)巨大的潜在优势和在超高频、超高速及低温应用领域的美好前景。本文考察了这种被称为第二代硅的新材料的生长技术及其在异质结双极晶体管中的应用,并简要介绍了国外在硅锗HBT研究方面的一些成果,展望了这种新型器件的发展前景。     

新的高性能硅锗异质器件结构

本文介绍硅锗技术在提高器件和电路性能方面的新发展,包括用于提高器件速度和低温下应用的硅锗异质结双极晶体管(HBT),以及用于提高PMOS管空穴迁移率的硅锗异质结构.     

应变硅NMOS晶体管沟道应变的模拟研究

建立了一种基于硅/锗硅异质结构的应变硅NMOS晶体管的有限元模型,通过模拟研究了沟道区的应变分布及其与器件参数的关系。结果表明,提高锗硅虚拟衬底中锗的摩尔组分、减小应变硅层厚度,可以增加沟道应变。此外,应变量还随器件结构长度的增加而增加。研究结果可为应变硅器件的设计、工艺优化提供参考依据。     

新型微电子器件及IC

评述了GaAs FET器件以后的新型微电子器件和IC的开发与研究现状,它们包括高电子迁移率晶体管、异质结双极晶体管、硅锗合金基区异质结双极晶体管、真空微电子器件、量子电子器件和光电集成电路.其中,有的已取得可观的实绩,巩固了阵地,有的虽然刚崭露头角,但却显示出雄厚的潜力.它们基本代表了半导体微电子器件未来的发展方向.     

硅锗基区异质结双极晶体管的研究进展

叙述了硅锗基区异质结双极晶体管的研究发展现状，分析了该晶体管的结构机理、特点及制造技术，并且阐述了该器件的发展前景。     

超高压SiGe HBT器件结构及制作工艺研究

介绍了一种超高压锗硅异质结双极晶体管(SiGe HBT)的器件结构及制作工艺。该器件增大了N型赝埋层到有源区的距离,采用厚帽层锗硅基区及低浓度发射区的制作工艺,以提高SiGe HBT的击穿电压;在基区和发射区之间利用快速热处理提高工艺稳定性,并使HBT的电流增益(β)恢复到原来水平,以弥补厚帽层锗硅基区及低发射区浓度造成的电流增益降低。基区断开时,发射区到集电区的击穿电压(BVCEO)提高至10V,晶体管特征频率达到20GHz。     

硅衬底微波集成电路

硅衬底微波集成电路具有诱人的发展前景。本文阐述了硅材料用作微波集成电路衬底的优点,分析了硅衬底微波传输线、无源元件以及锗硅异质结双极晶体管（SiGeHBT)的电性能,介绍了目前国外硅衬底微波集成电路研究的进展,并对数字电路与RF及微波电路在硅衬底上混合集成的特点与应用作了讨论。     

硅异质结和赝异质结双极器件研究进展

本文作者结合自己的工作，综述了硅异质结和赝异质结双极器件的研究进展，指出ＧｅＳｉ ＨＢＴ将成为双极结构的主流技术，硅赝异质结器件也将在低温应用等方面显示出优势。     

基于SGOI和CESL结构的新型应变硅NMOSFET的有限元研究

应变硅技术通过在沟道区引入适当的应变,达到提高载流子迁移率、改善MOS器件性能的目的.利用有限元法,研究了一种基于SGOI与氮化硅CESL应变结构的新型应变硅NMOSFET.结果表明,与采用单一的SGOI或CESL结构相比,两者共同作用下的新结构能更有效地提高沟道应变.增加氮化硅薄膜的本征应力、减小应变硅层厚度、适当提高锗组分,均能有效增加硅沟道区的应变量.采用有限元分析进行的模拟研究,可弥补实验测量的不足,为纳米级应变硅器件的设计和制造提供参考.     

新型发射极指组合结构功率SiGe HBT热分析

提出了一种发射极指分段和非均匀发射极指长、指间距组合的新型器件结构,以改善多指功率硅锗异质结双极晶体管(SiGe HBT)的热稳定性。考虑器件具有多层热阻,发展建立了相应的热传导模型。以十指功率SiGe HBT为例,运用有限元方法对其进行热模拟,得到三维温度分布。与传统发射极结构器件相比,新结构器件最高结温从416.3 K下降到405 K,各个发射指上的高低温差从7 K～8 K下降为1.5 K～3 K,热阻值下降14.67 K/W,器件整体温度分布更加均匀。     

SiGe器件及其研究综述

阐述了ＳｉＧｅ器件的主要研究方向以及国内外对ＳｉＧｅ材料和器件的研究情况,并对ＳｉＧｅ器件与Ｓｉ器件和ＧａＡｓ器件的发展前景进行了比较。     

采用低温Si技术的Si/SiGe异质结P-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。     

Excimer Laser‐Assisted In Situ Phosphorus Doped Si(1‐x)Gex Epilayer Activation

This paper presents results from experiments on laser‐annealed SiGe‐selective epitaxial growth (LA‐SiGe‐SEG). The SiGe‐SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA‐SiGe‐SEG technique with highly doped Ge and an ultra shallow junction on p‐type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA‐SiGe‐SEG technology is suitable for fabricating high‐speed, low‐power devices.     

Improving the Performance of SiGe Metal–Semiconductor–Metal Photodetectors by Using an Amorphous Silicon Passivation Layer

SiGe metal-semiconductor-metal photodetectors (MSM-PDs) with a thin amorphous silicon (a-Si:H) passivation layer have been fabricated by an ultrahigh-vacuum chemical vapor deposition (UHVCVD) system. It was found that the thin (30 nm) a-Si:H passivation layer could effectively suppress the dark current of SiGe MSM-PDs. As compared to the unpassivated devices, the dark current for devices with a-Si:H passivation layers was drastically reduced by 1.7 times 10⁵, and the photo-to-dark current ratio was enhanced by 1.33 times 10⁶. We attribute this result to the passivation effect of a-Si:H films on SiGe surfaces by hydrogen diffusion, which can compensate the dangling bonds on the SiGe surface.     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology

We developed a novel CMOS architecture that uses mechanical tensile stress, induced by the Si nitride-capping layer, together with the pseudomorphic compressive stress in SiGe layer to improve the drive current of both n- and pMOSFETs simultaneously. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that n- and pMOSFETs in the novel CMOS architecture behaved better in performance, not only a higher drain-to-source saturation current but also higher transconductance with wide gate voltage swing, than the Si-control devices, thus making this flow to show a great flexibility for developing next-generation high-performance CMOS.     

硅基异质集成技术发展趋势与进展

目前主流的异质集成技术有单片异质外延生长、外延层转移和小芯片微米级组装。硅基异质集成主要是指以硅材料为衬底集成异质材料(器件)所形成的集成电路技术。它首先在军用微电子研究中得到重视,并逐渐在民用领域扩展。硅基异质集成技术正处于芯片级集成向晶体管级集成的发展初期,已有关于晶体管级和亚晶体管级集成的报道。本文重点研究了单片三维集成电路(3D SoC)、太赫兹SiGe HBT器件、超高速光互连封装级系统(SiP)、单片集成电磁微系统等硅基异质集成技术前沿,展现了硅基异质集成技术的发展趋势,及其在军用和民用通信、智能传感技术发展中所具有的重要意义。     

调制掺杂层在SiGe PMOSFET中的应用

在普通Si器件性能模拟的基础上，详细研完了长沟应变SiGe器件的模拟，并进一步探讨了调制掺杂层的引入对器件性能(主要是跨导)的影响。在器件模拟过程中，采用隐含的SiGe材料和Si材料模型会得到与实际情况差别较大的结果。根据前人的材料研完工作，引入了插值所得的近似因子，以修正Silvaco中隐含的SiGe能带模型和迁移率参数。然后，依据修正后的模型对SiGe PMOS进行了更为精确的二维模拟，并验证了调制掺杂层的作用。     

Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.