Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults

The detection problem of bridging faults in AND-EXOR arrays is considered in this paper in a new framework. These AND-EXOR arrays are different from the arrays based on the so-called Reed-Muller canonic (RMC) expansion of functions. The multiple stuck-at fault detection test set in such arrays as already derived by Pradhan[1] has been utilized to detect bridging faults. One most important advantage of this test set is that it is independent of the function realized and it has a simple algebraic structure and hence can be generated easily. As this conventional test set is insufficient to detect all bridging faults, we propose a technique of augmenting the network with some additional observation points which take care of otherwise undetectable bridging faults.     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

ANALYZING MULTIPLE FAULTS IN SYNCHRONOUS SEQUENTIAL CIRCUITS BY BOOLEAN DIFFERENCE TECHNIQUES

The Boolean difference is a mathematical concept that has proved its usefulness in the study of single and multiple “stuck-at” faults in combinational circuits. Goldstein has extended his tool of analysis to cover the multiple stuck-at faults Asynchronous sequential circuits. In this paper, modifications to Goldstein's paper are presented, together with a new method for deriving the required shortest test sequence to detect a specified multiple fault.     

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faults

In this paper the problem of detecting bridging faults in two-dimensional (2-D) cellular logic arrays realizing an arbitrary Boolean function is considered in a new framework. A testable design of such combinational logic arrays has been proposed in which a set of universal tests can be initiated to detect all single stuck-at and bridging faults. The augmentation of the network for inducing testability is simple and is also independent of the function realized.     

Multiple detection test generation with diversified fault partitioning paths

The dependability of current and future nanoscale technologies highly depends on the ability of the testing process to detect emerging defects that cannot be modeled traditionally. Generating test sets that detect each fault more than one times has been shown to increase the effectiveness of a test set to detect non-modeled faults, either static or dynamic. Traditional n-detect test sets guarantee to detect a modeled fault with minimum n different tests. Recent techniques examine how to quantify and maximize the difference between the various tests for a fault. The proposed methodology introduces a new systematic test generation algorithm for multiple-detect (including n-detect) test sets that increases the diversity of the fault propagation paths excited by the various tests per fault. A novel algorithm tries to identify different propagating paths (if such a path exists) for each one of the multiple (n) detections of the same fault. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show the effectiveness of the approach in increasing the number of fault propagating paths when compared to traditional n-detect test sets.     

考虑逻辑门延时的冗余固定故障检测方法

提出利用瞬态电流测试(IDDT Testing)方法检测数字电路中的冗余固定故障。检测时采用双向量模式,充分考虑逻辑门的延时特性。针对两类不同的冗余固定故障,分别给出了激活故障的算法,在此基础上再对故障效应进行传播。SPICE模拟实验结果表明,该方法能有效地区分正常电路与存在冗余故障的电路,可以作为电压测试方法的一种有益的补充。     

Testable design of AND–EXOR logic networks with universal test sets

This paper presents a testability enhancement technique suited for AND–EXOR based logic networks that facilitates easy detection of stuck-at and bridging faults by a universal test set. Both cascaded and tree implementations of the EXOR-part are considered. The AND–EXOR based circuit implemented with a cascaded EXOR-part requires a universal test set of size (2n + 6) for an n-variable function implementation. For Generalized Reed–Muller (GRM) implementation, this test set detects all single stuck-at and bridging faults (both OR-type and AND-type) and also large number of multiple bridging faults. For an Exclusive-OR Sum-of-Products (ESOP) implementation, a few single bridging faults may remain untested under this test set, occurrence of which can be minimized by employing an appropriate design and layout technique. Next, it is shown that an AND–EXOR network with a tree-based EXOR-part can be tested for similar faults by a universal test set of size (2n + 8). This paper also solves an open problem of designing a universal test for a tree-based AND–EXOR circuit. Since the EXOR-tree has depth of (log₂s+1), where s is the number of product terms in the given AND–EXOR expression, this tree-based design reduces the circuit delay significantly compared to cascaded EXOR implementation. In both the cases, the test set can be stored in a ROM on-chip for built-in self-test (BIST) purposes. For several benchmark circuits, the universal test set is found to be much smaller in size than the ATPG-generated test sets.     

集成电路高层故障模型间关系分析方法

集成电路的测试变得日益重要，传统的门级测试虽然效果很好，但是随着电路规模的增大而面临着测试时间太长的困境．高层测试可以很好地缓解测试时间过长的问题，但最大的困难是缺少恰当的故障模型．通过对高层故障模型与门级固定型故障模型间关系可以建立高层故障模型的评估规则。在该规则下可以再对高层故障模型间关系进行分析，以确定彼此间的覆盖关系．归纳模型间的互相覆盖以确定彼此是否包含，这有助于对高层故障模型进行评估，寻找能够对应逼近门级固定型（stuck-at）故障模型的高层故障模型序列，该模型序列有望指导新的测试生成．最后，以对ITC99中标准时序电路的实验来说明该理论方法．     

A statistical model for delay-fault testing

The authors propose a statistical model for measuring delay-fault coverage. The model provides a figure of merit for delay testing in the same way that fault coverage provides one for the testing of single stuck-at faults. The mode measures test effectiveness in terms of the propagation delay of the path to be tested, the size of the delay defect, and the system clock interval, and then combines the data for all delay faults to measure total delay-fault coverage. The authors also propose a model for measuring the defect level as a function of the manufacturing yield and the predictions of the statistical delay-fault coverage model     

大规模数字集成电路标准矩阵功能测试新方法

本文提出了一种对VLSI电路功能测试的方法,可以同时检测和定位VLSI电路输入和输出端上的固定故障和桥接故障,而不需要知道它们的内部逻辑结构。因而,对于简化测试过程、降低测试成本,具有十分重要的实际意义。     

IIR滤波器的测试及可测性设计

基于加法器测试生成,提出了无限脉冲响应(IIR)滤波器的一种通用可测性设计、测试方案.在测试模式下,通过切断IIR滤波器中的反馈回路提高了该设计的可测性.通过复用原电路中的部分寄存器和加法器来提高其可测性,降低了额外的测试硬件面积开销.该方法能在真速下高效地侦测到IIR滤波器基本组成单元内的任意固定型组合失效,没有降低电路性能.     

延迟计时滞回比较器在发动机故障检测中的应用研究

在试飞中利用发动机状态实时智能监视软件对发动机故障进行实时自动检测时,比较器是不可缺少的元件。但是鉴于试飞中遥测数据有时会同时受到毛刺和跳点干扰,因此,单门限比较器和滞回比较器不能满足使用要求。延迟计时滞回比较器在滞回比较器的基础上增加了一个延迟计时器,具有与滞回比较器一样的抗毛刺干扰能力。此外,延迟计时滞回比较器对跳点干扰同样是免疫的,具有很好的鲁棒性。     

A Hardware Artificial Immune System and Embryonic Array for Fault Tolerant Systems

Nature demonstrates amazing levels of fault tolerance; animals can survive injury, damage, wear and tear, and are under continual attack from infectious pathogens. This paper details inspiration from biology to provide fault tolerant electronic circuits. An artificial immune system (AIS) is used to detect faults and an embryonic array to quickly reconfigure around them. The AIS makes use of a negative selection algorithm to detect abnormal behaviour. The embryonic array takes its inspiration from the development of multi-cellular organisms; each cell contains all the information necessary to describe the complete individual. Should an electronic cell fail, its neighbours have the configuration data to take over the failed cell's functionality. Two demonstration robot control systems have been implemented to provide a Khepera robot with fault tolerance. The first is very simple and is implemented on an embryonic array within a Virtex FPGA. An AIS is also implemented within the array which learns normal behaviour. Injected stuck-at faults were detected and accommodated. The second system uses fuzzy rules (implemented in software) to provide a more graceful functionality. A small AIS has been implemented to provide fault detection; it detected all faults that produced an error greater than 15% (or 23% off straight).     

Defect-oriented testing and defective-part-level prediction

After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis     

Online testing approach for very deep-submicron ICs

Very deep-submicron technologies pose new challenges to IC testing. In particular, crosstalk and transient faults are difficult to detect with traditional methods. Online testing techniques can detect these faults, however, and a new approach extends these techniques to include gross-delay faults. Moreover, this approach described by the authors can be exploited to detect stuck-at and bridging faults offline     

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.     

固定型故障完全可测异步控制电路设计

本文基于直接映射技术和异步控制电路的故障自检测特性,提出了一种固定型故障完全可测的异步控制电路设计方法,并在此基础上对异步控制电路单固定型故障的测试策略进行了较为详细的阐述。结果表明本方法切实有效且额外的面积开销小。     

Gate-delay-fault testability properties of multiplexor-based networks

We investigate the gate-delay-fault testability properties of multilevel, multiplexor-based logic circuits. Based on this investigation, we describe a procedure for synthesizing gate-delay-fault testable multilevel circuits. The procedure involves the construction of a multilevel circuit from a general, unordered Binary Decision Diagram (BDD) by replacing vertices of the BDD with multiplexors. The procedure relies on the following result derived in this article: If the multilevel circuit constructed from the BDD is initially fully single stuck-at fault testable, or made fully single stuck-at fault testable by redundancy removal, then it is completely robustly gate-delay-fault testable. Once the initial gate-delay-fault testable circuit has been obtained, constrained algebraic factorization is used to improve the area and performance characteristics without compromising testability. Unlike previous techniques for synthesizing robustly gate-delay-fault testable circuits, this procedure can be used to synthesize fully testable circuits directly from nonflattenable, logic-level implementations.     

FPGA状态机在多路异步串口通信处理的实时优势

首先简要介绍了异步串口板的通常设计方法,并且提出了这些方法的不足之处,重点阐述了基于FPGA状态机和片上总线的新设计方案,以及该方案的技术优势,随后公布了基于该方案的异步串口板达到的性能指标;通过比较有关应答延迟的试验数据,提出了基于FPGA状态机和基于DSP处理器的异步串口板卡存在明显的处理速度差异问题,并基于两种设计方案,解释了形成差异的原因;最后提出了FPGA状态机对外部总线存储器或端口的访问管理性能大幅超越了任何一款DSP处理器的观点,并对同行提出了类似研发项目的设计建议。     

Near-minimal test sets for the detection of single gate faults

A new algorithm is presented for the detection of single gate faults in combinational networks. A gate fault is any unknown transformation of the Boolean function realized by a particular gate or single-output subnetwork. Detection of such faults is accomplished by verifying the truth table of the correct gate function.The concept of real transform of a Boolean function is utilized to obtain in each iteration an optimal test, namely, a test that performs as much of the fault detection task as possible. The resulting test set is near-minimal and complete.The algorithm can handle multi-output networks, integrated network components and mixed (gate, stuck-at) fault models.