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1.
1~7GHz全单片低噪声放大器   总被引:4,自引:1,他引:3  
一种性能优异的全单片宽带低噪声反馈放大器已研制成功。此两级放大器的特点是 ,性能稳定 ,频带宽 ,噪声低 ,增益高而平坦 ,可直接由 +5 V单电源供电 ,无需外加偏置电路 ,输入输出由 MIM电容隔直 ,使用方便。它由栅长为 0 .5 μm Ga As工艺制作而成 ,所有电路元器件皆集成在 3 .0 mm× 2 .0 mm的 Ga As衬底上。经测量 ,在频率 1~ 7GHz的范围内 ,放大器增益大于 2 0 d B,带内增益波动小于± 0 .75 d B,噪声系数 NF<2 .5d B,输入输出驻波 VSWR约 2 .0 ,1分贝压缩点输出功率大于 1 4d Bm。文中介绍了放大器的设计原理和工艺过程 ,并给出了测量结果。测量结果与设计符合得很好。最后值得指出的是 76mm Ga As圆片的成品率高 ,性能一致性好。  相似文献   

2.
In this paper, we present the results of RF and noise measurements of MESFETs transplanted by epitaxial lift off (ELO). ELO is a technology by which epitaxially grown layers are lifted off from their growth substrate and subsequently reattached to a new host substrate. In the experiments described here a 800 mm thick GaAs film containing MESFETs or complete microwave circuits is transplanted onto semi-insulating InP. Gate leakage current, RF characteristics, and noise performance of MESFETs and GaAs circuits are compared before and after ELO. Special attention was given to low-frequency (1/f) noise, 1/f noise is believed to be caused by surface as well as bulk effects. An increase in 1/f noise could have been predicted since a new surface is exposed during the transplantation process. The mechanical stress during the transplantation could cause crystal damage creating additional traps which could also result in an increase in 1/f noise  相似文献   

3.
GaAs/tungsten Schottky barrier mixer diodes have been fabricated in a self-passivated, grown guard layer configuration. These devices have exhibited 0.64 eV barrier voltages together with the ability to withstand nanosecond RF pulses in excess of 8 ergs with no resulting deterioration in noise figure performance. Such high burnout resistance properties are attributed to the absence of any significant metallurgical interaction between the GaAs and tungsten at temperatures as high as 600°C. The somewhat high noise figures exhibited by these devices are attributed to interface states, possibly arising from strain.  相似文献   

4.
5.
An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm2 . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm2 GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm 2 GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900  相似文献   

6.
用于先进 CMOS电路的 150 mm硅外延片外延生长   总被引:3,自引:3,他引:0  
随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,  相似文献   

7.
The CW performance of GaAs transferred electron oscillators (TEO) is described. The TEO were fabricated from n+-n-n+epitaxial structures of GaAs grown from the vapor phase. The devices consisted of single mesas, 5-6 mil in diameter, on plated silver heat sinks. Fifteen devices were fabricated from three separate wafers and the results were very uniform. The dc to RF efficiency varied between 4 and 5.7 percent for the 15 devices packaged and tested. The best results were 350 and 390 mW of RF power with a conversion efficiency of 5.4 and 5.7 percent, respectively, at approximately 17.5 GHz from single 5.5-mil mesas. These data represent new highs in performance from single-mesa TEO at this frequency. The results indicate that vapor epitaxial growth procedures combined with a device fabrication scheme based on plated heat sink technology can yield reproducible TEO with RF powers greater than 250 mW at efficiencies greater than 5 percent. The results indicate also that the plated heat sink approach will be useful for other devices, such as IMPATTS, in which thermal considerations limit device performance.  相似文献   

8.
GaAs亚微米自对准工艺技术研究   总被引:2,自引:2,他引:0  
总结了在50mmGaAs圆片上实现自对准介质膜隔离等平面工艺技术的研究,着重描述了离子注入、自对准亚微米难熔栅制备、钝化介质膜生长、干法刻蚀、电阻和电容制备等关键工艺的研究结果。这套工艺的均匀性、重复性好,在50mmGaAs圆片上获得了满意的成品率。采用这套工艺已成功地研制出多种性能良好的GaAsIC和GaAs功率MESFET,证明国家自然科学基金委员会这一重大课题的选择对发展我国GaAsIC确实具有重大意义。  相似文献   

9.
The development of optical transmission calls for sensitive and fast optoelectic transducers. With the advent of optical local area networks, hybrid transducers may no longer be appropriate, and monolithic emitters and receivers will be preferred. In this paper, we report on the first monolithic photoreceiver implemented with GaAs-GaAIAs bipolar devices. One phototransistor and two transistors are integrated, together with four resistors on a 0.5x0.5-mm/sup 2/ GaAs chip. The transimpedance receiver has a bandwidth of 80 MHz. SignaI and noise power measurements indicate that for a digital signal at 140 Mbit/s, the minimum detectable power is 1 µW (-30 dBm).  相似文献   

10.
A well-established characterization method for investigating deep traps in semi-insulating (SI) GaAs is thermally stimulated current (TSC) spectroscopy; however, TSC is not considered to be a quantitative technique because it involves carrier mobility, lifetime, and geometric factors, which are either unknown or poorly known. In this paper, we first show how to quantify a TSC spectrum, by normalizing with infrared (hv = 1.13 eV) photocurrent, and then apply this method (called NTSC) to study the lateral uniformity of the main deep centers across the diameters of undoped SI GaAs wafers. The wafers used in the study include both the standard 100 mm sizes and the new 150 mm variations, and are grown by both the low and high pressure liquid encapsulated Czochralski techniques. The results reveal that the 150 mm wafers have a worse NTSC uniformity for the main traps and a higher degree of compensation, as compared these parameters for the 100 mm wafers. In addition, nonuniformities related to the electric field effects on both the TSC spectrum and the low temperature photocurrent are found in the 150 mm wafer grown by the low pressure technique.  相似文献   

11.
Ka-band GaAs FET's with power output in excess of 200 mW and with efficiencies of more than 20 percent are described. Both ion-implanted and VPE-grown wafers were used. Deep UV (300-nm) lithography and chemical etching was employed to obtain a final gate length of 0.5 µm. These FET chips were flip-chip mounted and had a very low thermal resistance of 50°C/W for a total source periphery of 0.6 mm. At 35 GHz an output power of 220 mW with 21-percent efficiency at 3-dB gain was obtained from a 0.6-mm cell.  相似文献   

12.
The rapidly improving performance of low-noise GaAs FET's can to a large extent be attributed to advances in the material preparation technology. Ion implantation directly into bulk-grown semi-insulating substrate material represents an optimum approach by providing excellent control and reproducibility over the doping parameters in the active layer. This paper will review development efforts carried out to capitalize on these inherent advantages and discuss the results obtained from transistors fabricated by this method. Device modeling has been used to investigate the effects of profile tailoring and has served as a guide for selecting implant species, doses, and energies. This effort has paralleled the development of the implantation technology, which has addressed the problems of selecting suitable substrate material, deposition of suitable capping material for the post-implantation anneal, the study of doping profiles, and the diffusion during the anneal. The advances made in these areas will be discussed along with the fabrication procedures for the low-noise FET's. Favorable doping profiles were obtained by using Se implants as evidenced by the small variation in the measured transconductance versus gate voltage. The excellent uniformity and reproducibility obtained in the active layer parameters have resulted in tightly distributed transconductances, pinchoff voltages, and S-parameters. Measured parameters from five wafers have given typical standard deviations of less than 10 percent of the mean value. Packaged transistors with a nominal gate length of 1 µm have yielded noise figures of 1.1 dB at 4 GHz with 12- dB associated gain, while 2.5-dB noise figures have been achieved at 15 GHz with 7-dB gain from transistors mounted on a low parasitic carrier. These improved RF results combined with a high level of reproducibility present ion implantation as a very attractive method for fabricating low-noise GaAs FET's.  相似文献   

13.
Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.  相似文献   

14.
We report on electrical characterization and uniformity measurements of the first conventionally processed AlGaN/GaN high electron mobility transistors (HEMTs) on free-standing chemical-vapor-deposited (CVD) diamond substrate wafers. DC and RF device performance is reported on HEMTs fabricated on $sim!!hbox{130-}muhbox{m}$-thick and 30-mm round CVD diamond substrates without mechanical carrying wafers. A measured $f_{T} cdot L_{G}$ product of 12.5 $hbox{GHz} cdot muhbox{m}$ is the best reported data for all GaN-on-diamond technology. X-band power performance of AlGaN/GaN HEMTs on diamond is reported to be 2.08 W/mm and 44.1% power added efficiency. This letter demonstrates the potential for GaN HEMTs to be fabricated on CVD diamond substrates utilizing contact lithography process techniques. Further optimization of the epitaxy and diamond substrate attachment process could provide for improvements in thermal spreading while preserving the electrical properties.   相似文献   

15.
Quasioptical 2-mm and 1,5 mixer receivers for room temperature operation are described. Receivers incorporates polarization-rotationing dual-beam interferometers, used as antenna-heterodyn diplexer, waveguide Schottky diode mixers, carcinotron (BWO) and carcinitron with the frequency doubler, used as local oscillators (LO), and GaAs IF amplifiers. The best receiver noise temperatures are 600K (DSB) at 2,0-mm and 800K (DSB) at 1,5-mm wavelengths bands. The performance of these receivers is also discussed.  相似文献   

16.
在L EC Ga As晶片中,存在相当大的弹性应变,在高温退火后,晶片的晶格参数的相对变化量不到原生晶片的70 % ,残余应力得以部分释放,从而减小残余应力诱生断裂的可能性,提高了Ga As晶体的断裂模数.原生Ga As晶体加工的样品的断裂模数平均值约为135 MPa,而退火Ga As晶体加工的样品的断裂模数平均值更高,约为15 0 MPa,断裂模数最高值达16 3MPa.  相似文献   

17.
Instantaneous gain, noise figure, reverse attenuation, and gain and phase control measurements in the frequency range 8-18 GHz have been performed on GaAs traveling-wave transistors. The broad-band high-gain nature of the device together with the requirement for several bias connections precluded the use of standard test fixtures, and resulted in a package design exhibiting less than 1-dB insertion loss over the band together with 75- to 90-dB internal isolation. Untuned X-band gain, noise figure, and reverse attenuation were 12 dB, 18 dB, and 32 dB, respectively, and the gain and phase could be electronically varied over a 35-dB and 360/spl deg/ range. When RF tuning was employed, the gain, on the average, improved by 10 dB.  相似文献   

18.
A capless annealing method for GaAs, employing short (1-10-s) thermal heat pulses from a graphite strip heater, is described. Results with29Si+ implanted into semi-insulating chromium-doped HB and chromium-doped LEC GaAs are presented. The samples were annealed at temperatures as high as 1000°C in a stationary N2atmosphere with the implanted surface in close contact with a flat graphite strip heater surface. The wafers were covered with a graphite lid, effectively confining the volatile arsenic to a very small volume around the sample and providing a uniform temperature environment. Implantation efficiencies were high, and the quality of the implanted surface remained excellent after annealing.  相似文献   

19.
Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.  相似文献   

20.
阐述了毫米波段低噪声GaAsPHEMT课题的研究过程,报道了研究结果。研制出的器件最高振荡频率超过150GHz,这是国内第一个频率进入3毫米波段的半导体三端有源器件。在Ka波段有优良的噪声和增益性能。  相似文献   

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