一种基于伪循环MDS码的准循环LDPC码构造方法

该文提出了一种利用两个信息符号的伪循环最大距离可分(MDS)码,构造围长为6的准循环低密度奇偶校验(LDPC)码的方法。在GF(q)中,它通过直接计算长为q+1的伪循环MDS码生成多项式,构造准循环LDPC码的校验矩阵。其主要利用了含两个信息符号的伪循环MDS码字特殊的循环性,及任意两个码字间距离不小于q的特点,使所构造的准循环LDPC码保证无4环。仿真结果表明,基于伪循环MDS码的准循环LDPC码在高斯信道下,能获得较好的误码性能。     

基于素域构造的准循环低密度校验码

该文提出一种基于素域构造准循环低密度校验码的方法。该方法是Lan等所提出基于有限域构造准循环低密度校验码的方法在素域上的推广,给出了一类更广泛的基于素域构造的准循环低密度校验码。通过仿真结果证实:所构造的这一类准循环低密度校验码在高斯白噪声信道上采用迭代译码时具有优良的纠错性能。     

一种用于短猝发通信的LDPC短码设计

介绍了用于构建大围长Tanner图的PEG构造方法及可用于构造准循环校验矩阵的改进算法。由于短环是影响LDPC短码性能的主要因素,必须尽量增大最小短环的围长并减少短环的数量,以获得最大的平均围长。针对短猝发通信需求,构造了一种基于PEG算法的码长较短的准循环LDPC码。计算机仿真表明其性能优异,在通用硬件平台上对其中频传输性能进行了测试,测试结果满足短猝发通信对误码率的要求。由于该短码性能较好,电路实现复杂度低,延时小,适用于短猝发通信。     

基于初等数论的圈长8规则准循环LDPC码

This paper is concerned with (3, n ) and (4, n ) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory. Given the column weight, we determine the shift values of the circulant permutation matrices via arithmetic analysis. The proposed constructions of quasi-cyclic LDPC codes achieve the following main advantages simultaneously: 1) our methods are constructive in the sense that we avoid any searching process; 2) our methods ensure no four or six cycles in the bipartite graphs corresponding to the LDPC codes; 3) our methods are direct constructions of quasi-cyclic LDPC codes which do not use any other quasi-cyclic LDPC codes of small length like component codes or any other algorithms/cyclic codes like building block; 4)the computations of the parameters involved are based on elementary number theory, thus very simple and fast. Simulation results show that the constructed regular codes of high rates perform almost 1.25 dB above Shannon limit and have no error floor down to the bit-error rate of 10-6 .     

基于多重置换阵的满秩结构化LDPC码构造方法

 在多重置换阵的基础上,提出一种适用基于网络编码的协作中继策略的结构化LDPC码构造方法.首先定义了多重置换阵的概念,提出并证明了该方阵在秩和消元等方面的重要性质;给出具体的构造步骤,构造了列重为3和围长至少为6的满秩LDPC码;分析了该LDPC码的生成矩阵,具有稀疏和结构化的特点,适用基于网络编码的协作中继系统中进行联合网络编码和迭代译码.仿真结果表明,在相同码长、2/3码率和准循环矩阵 Y 结构条件下,相比阵列LDPC码、近似双对角形式的LDPC码和三对角形式的LDPC码,新构造的LDPC码具有相对较好的译码性能.     

Window-constrained interconnect-efficient progressive edge growth LDPC codes

One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature of their iterative belief propagation decoding, making them amenable to efficient hardware implementation. However, for an arbitrary code construction, the random-like connections between the code's Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem of dense connections between processing nodes. The approach is based on controlling the maximum connection length between processing nodes in order to make fully parallel implementation feasible. The proposed algorithm offers a good compromise between error correction performance and decoder complexity. Simulation results and FPGA-based implementation comparisons are presented to demonstrate the advantages of the proposed LDPC code constructions, and it is shown that, with proper window-constrained node placement design, an improvement of up to 40% in interconnect efficiency is achievable without any significant degradation in error correction capability.     

基于串行消息传递机制的QC-LDPC码快速译码算法研究

针对准循环LDPC(QC-LDPC)码基于洪水消息传递机制译码算法的不足,该文提出了一种快速的分组串行译码算法。该算法通过将LDPC码的校验节点(或变量节点)按一定规则划分成若干个子集,在每一轮迭代过程中,依次对各个子集中的校验节点(或变量节点)并行地进行消息更新,提高了译码速度。同时根据分组规则,提出了一种有效的分组方法,并通过分析发现基于循环置换阵的准循环LDPC码非常适合采用这种分组译码算法进行译码。通过对不同消息传递机制下准循环LDPC码译码算法性能的仿真比较,验证了在复杂度不增加的情况下,该译码算法在继承了串行译码算法性能优异和迭代收敛快等优点的同时,极大地提高了准循环LDPC码的译码速度。分析表明,分组串行译码算法译码速度至少为串行译码算法的p倍(p为准循环LDPC码校验矩阵中循环置换阵的行数或列数)。     

800Mbps准循环LDPC码译码器的FPGA实现

本文提出了一种适用于准循环低密度校验码的低复杂度的高并行度译码器架构。通常准循环低密度校验码不适于设计有效的高并行度高吞吐量译码器。我们通过利用准循环低密度校验码的奇偶校验矩阵的结构特点,将其转化为块准循环结构,从而能够并行化处理译码算法的行与列操作。使用这个架构,我们在Xilinx Virtex-5 LX330 FPGA上实现了(8176,7154)有限几何LDPC码的译码器,在15次迭代的条件下其译码吞吐量达到800Mbps。      

几种LDPC码的最小汉明距离的计算

本文提出一种计算LDPC码的真实最小汉明距离的方法．该方法能够用来计算多种LDPC码方案的真实最小汉明距离，比如准循环LDPC码、pi-旋转LDPC码等．该方法是通过计算码的环长间接地找到LDPC码最小距离，由于计算环长的计算量要远比直接计算最小汉明距离来得低，因而该算法能够在有限时间内找到LDPC码的真实最小距离．通过仿真表明，用目前主流的个人计算机利用该方法找出一个有最小距离24的码率为1／4的准循环LDPC码最小距离大概需要花77分钟。     

Construction of Irregular LDPC Codes by Quasi-Cyclic Extension

In this correspondence, we propose an approach to construct irregular low-density parity-check (LDPC) codes based on quasi-cyclic extension. When decoded iteratively, the constructed irregular LDPC codes exhibit a relatively low error floor in the high signal-to-noise ratio (SNR) region and are subject to relatively few undetected errors. The LDPC codes constructed based on the proposed scheme remain efficiently encodable     

任意列重大围长QC-LDPC码的确定性构造

针对准循环低密度奇偶校验（Quasi-Cyclic Low-Density Parity-Check,QC-LDPC）码中准循环基矩阵的移位系数确定问题,提出基于等差数列的确定方法.该方法构造的校验矩阵围长为8,列重可任意选取,移位系数由简单的数学表达式确定,编码复杂度与码长呈线性关系,节省了编解码存储空间.研究结果表明,列重和围长是影响码字性能的重要因素.在加性高斯白噪声（Additive White Gauss Noise,AWGN）信道和置信传播（Belief Propagation,BP）译码算法下,该方法构造的码字在短码时可以获得与IEEE 802.11n、802.16e码相一致的性能,在长码时误比特率性能接近DVB-S2码.同时表明该方法对码长和码率参数的设计具有较好的灵活性.     

高码率短码长两边类型LDPC码的设计

高码率LDPC（10w．densityparity-check）码的设计一直是当前纠错编码领域的难点,尤其在短码长情况下。近年被提出的两边类型LDPC（tow—edgetypeLDPC,TET-LDPC）码在高码率情况下具有比传统LDPC码更加优秀的纠错性能。基于对TET—LDPC码结构优势的分析,文中提出一种优化设计方法,该方法通过合理选取TET．LDPC码中删余变量节点的度以及优化校验节点和变量节点的连接关系,进一步提高了该码型的性能。仿真结果显示,在AWGN信道下,文中设计的高码率短码长TET—LDPC码,不仅好于传统LDPC码,而且也好于传统的TET-LDPC码,具有更低的误码平台。     

A Unified Approach to the Construction of Binary and Nonbinary Quasi-Cyclic LDPC Codes Based on Finite Fields

A unified approach for constructing binary and nonbinary quasi-cyclic LDPC codes under a single framework is presented. Six classes of binary and nonbinary quasi-cyclic LDPC codes are constructed based on primitive elements, additive subgroups, and cyclic subgroups of finite fields. Numerical results show that the codes constructed perform well over the AWGN channel with iterative decoding.     

Systematic recursive construction of LDPC codes

This letter presents a systematic and recursive method to construct good low-density parity-check (LDPC) codes, especially those with high rate. The proposed method uses a parity check matrix of a quasi-cyclic LDPC code with given row and column weights as a core upon which the larger code is recursively constructed with extensive use of pseudorandom permutation matrices. This construction preserves the minimum distance and girth properties of the core matrix and can generate either regular, or irregular LDPC codes. The method provides a unique representation of the code in compact notation.     

A novel construction of quantum ldpc codes based on cyclic classes of lines in euclidean geometries

The dual-containing (or self-orthogonal) formalism of Calderbank-Shor-Steane (CSS) codes provides a universal connection between a classical linear code and a Quantum Error-Correcting Code (QECC). We propose a novel class of quantum Low Density Parity Check (LDPC) codes constructed from cyclic classes of lines in Euclidean Geometry (EG). The corresponding constructed parity check matrix has quasi-cyclic structure that can be encoded flexibility, and satisfies the requirement of dual-containing quantum code. Taking the advantage of quasi-cyclic structure, we use a structured approach to construct Generalized Parity Check Matrix (GPCM). This new class of quantum codes has higher code rate, more sparse check matrix, and exactly one four-cycle in each pair of two rows. Experimental results show that the proposed quantum codes, such as EG(2,q)II-QECC, EG(3,q)II-QECC, have better performance than that of other methods based on EG, over the depolarizing channel and decoded with iterative decoding based on the sum-product decoding algorithm.     

Construction of nonbinary cyclic, quasi-cyclic and regular LDPC codes: a finite geometry approach

This paper presents five methods for constructing nonbinary LDPC codes based on finite geometries. These methods result in five classes of nonbinary LDPC codes, one class of cyclic LDPC codes, three classes of quasi-cyclic LDPC codes and one class of structured regular LDPC codes. Experimental results show that constructed codes in these classes decoded with iterative decoding based on belief propagation perform very well over the AWGN channel and they achieve significant coding gains over Reed-Solomon codes of the same lengths and rates with either algebraic hard-decision decoding or Kotter-Vardy algebraic soft-decision decoding at the expense of a larger decoding computational complexity.     

LDPC block and convolutional codes based on circulant matrices

A class of algebraically structured quasi-cyclic (QC) low-density parity-check (LDPC) codes and their convolutional counterparts is presented. The QC codes are described by sparse parity-check matrices comprised of blocks of circulant matrices. The sparse parity-check representation allows for practical graph-based iterative message-passing decoding. Based on the algebraic structure, bounds on the girth and minimum distance of the codes are found, and several possible encoding techniques are described. The performance of the QC LDPC block codes compares favorably with that of randomly constructed LDPC codes for short to moderate block lengths. The performance of the LDPC convolutional codes is superior to that of the QC codes on which they are based; this performance is the limiting performance obtained by increasing the circulant size of the base QC code. Finally, a continuous decoding procedure for the LDPC convolutional codes is described.     

一种高码率低复杂度准循环LDPC码设计研究

该文设计了一种特殊的高码率准循环低密度校验(QC-LDPC)码,其校验矩阵以单位矩阵的循环移位阵为基本单元,与随机构造的LDPC码相比可节省大量存储单元。利用该码校验矩阵的近似下三角特性,一种高效的递推编码方法被提出,它使得该码编码复杂度与码长成线性关系。另外,该文提出一种分析QC-LDPC码二分图中短长度环分布情况的方法,并且给出了相应的不含长为4环QC-LDPC码的构造方法。计算机仿真结果表明,新码不但编码简单,而且具有高纠错能力、低误码平层。     

基于一些PBIBD的低密度校验码的构造

本文构造了两类部分平衡不完全区组设计.并利用它们构造了一类低密度校验码(LDPC码),其最小环长至少为6,码率的选取具有很大的灵活性,而且可以具有拟循环结构.计算机仿真结果表明这种方法构造的LDPC码,在加性高斯白噪声信道中BPSK调制下用和积迭代译码性能很好.     

Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.