New Feedback Architecture for VCO-Based Delta-Sigma ADCs Utilizing Phase Shifter

The voltage controlled oscillator-based （VCO-based） continuous-time delta-sigma （CTDS） analog to digital converter （ADC） suffers from nonlinearity and mismatch in its feedback network. A new feedback network consisting of a phase shifter is proposed. The phase shifter replaces the digital to analog converter （DAC） in the proposed architecture. Feasibility of the proposed idea is discussed and its higher performance is illustrated through a behavioral simulation approach （CppSim）. We have also developed the phase shifter as a variable all-pass filter in the C language. The nonlinearity and mismatch of the system caused by DAC is mitigated, resulting in higher signal to noise ratio （SNR） and signal to noise and distortion ratio （SNDR）, respectively.     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

基于Quartet测试系统的高速DAC芯片测试

介绍了通用DAC芯片的主要测量参数及其测试方法。并以12-bit高速DAC芯片ISL5861为例,利用Credence公司的数模混合信号测试系统Quartet实现对高速数模转换芯片进行测试。     

一种带斐波那契译码的高精度电流舵DAC

在设计的电流舵DAC中应用了一种新的译码结构,即斐波那契数列译码结构。通常电流舵DAC设计基于面积和精度的折衷考虑,会采用高位温度计译码,低位二进制译码的分段结构,在此设计的电流舵DAC为进一步提高精度,高位6位仍采用温度计译码,低6位用斐波那契数列译码代替二进制译码。仿真测得DAC转换器的积分非线性误差（INL）为0.5 LSB,微分非线性误差（DNL）为0.28 LSB。在10 MHz采样率下,无杂散动态范围（SFDR）达85 dB。     

为GSM／EDGE选择DAC

概述随着无线通信标准（宽带、多载波）的发展与完善，对于系统低失真、低噪声指标的要求也更加严格。这类系统中，发送器（Tx）采用的数字/模拟转换器（DAC）是模拟信号发生器的关键部件，直接决定了系统的动态特性。GSM/EDGE多载波基站发送器的设计者为那些制造通信DAC的厂商提出了苛刻的指标，要求在更高的输出频率下提供更高的分辨率和更快的刷新速率，同时还要在整个频带内降低噪声和信号失真。根据上述要求，GSM/EDGE设计人员只对那些满足下述四个关键指标的通信DAC感兴趣：a）无杂散动态范围（SFDR）；b）信噪比（SNR）…     

The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain

At present,the architecture of a digital-to-analog converter（DAC） in essence is based on the weight current,and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase,which is 2^n-1 times of its least weight current.But for a dual weight resistance chain type DAC,by using the weight voltage manner to D/A conversion,the D/A signal current is fixed to chain current I_cha;it is only 1/2^n-1 order of magnitude of the average signal current value of the weight current type DAC.Its principle is:n pairs dual weight resistances form a resistance chain,which ensures the constancy of the chain current;if digital signals control the total weight resistance from the output point to the zero potential point,that could directly control the total weight voltage of the output point,so that the digital signals directly turn into a sum of the weight voltage signals;thus the following goals are realized:（1） the total current is less than 200μA;（2） the total power consumption is less than 2 m W;（3） an 18-bit conversion can be realized by adopting a multi-grade structure;（4） the chip area is one order of magnitude smaller than the subsection current-steering type DAC;（5） the error depends only on the error of the unit resistance,so it is smaller than the error of the subsection current-steering type DAC; （6） the conversion time is only one action time of switch on or off,so its speed is not lower than the present DAC.     

高速高精度DAC关键性能测试方法研究

本文介绍了高速高精度DAC的测试方法,并针对测试中遇到的具体问题,提出了在测试动态参数方面的解决办法,而且以实际测试证明了该方法的有效性。     

一种16位电流舵DAC的高精度前台校准方法

基于28 nm CMOS工艺,采用一种高精度的前台校准技术设计了一款16 bit电流舵数模转换器（Digitalto-analog converter,DAC）电路。该前台校准算法对16 bit数据对应的所有电流源进行校准,并且使用的电流源只有两种大小,降低校准难度的同时也提升了校准的精度。该校准电路引入了两种校准补充电流,分别用于温度和输出电流变化引起电流源失配的补偿,进一步减小了DAC电流源的失配,有效提高了DAC的整体性能。采用校准后,在-40～85℃温度范围内,微分非线性≤0.8 LSB,积分非线性≤2.0 LSB,200 MHz输出信号下无杂散动态范围≥75.3 dB。该校准方法提高了DAC的温度稳定性。     

滤波器在音频DAC测试中的应用

本文给出了模拟滤波器在使用ATE（Automatic Test Equipment自动测试设备）进行高精度音频DAC（数模转换器）测试中的应用,该方法提高了测试准确度,满足了芯片量产测试的需求。论文首先介绍了DAC在ATE上的基本测试方法,然后讨论了应用滤波器的音频DAC测试方案,最后通过Matlab数学仿真和搭建电路对实际的芯片进行测试,证明了该方案的有效性。     

一个18位高性能音频Σ-Δ数模转换器

本文介绍了一个采用多比特量化的高性能音频Σ-Δ数模转换器。相对于单比特量化的Σ-Δ DAC来说,多比特量化具有调制器环路设计简单、时钟频率低、杂波小等优点;而由多比特量化引入的失配误差,可以采用DWA误差整形算法,将其转换为高频段噪声外推到信号带外,使带内的噪底降低到单比特量化的水平。为减弱数模串扰,进行了对每个模拟元件都加上保护环的创新尝试。采用上述技术在0.18μm混合信号CMOS工艺上实现了一个18位DAC,芯片面积1.86 mm2。测试结果表明,数模转换器的信噪失真比(SNDR)和动态范围（DR）分别达到88dB和96dB。     

10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating

This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with V_DD=1.2 V. Its area is 0.21 mm². It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.     

DAC8831在恒电位仪电压扫描中的应用

为实现恒电位仪给定电压低速扫描时电压高精度、线性好及降低设计成本,设计了一种简单可行的电压扫描系统。该系统以STC89C51为主控器件,通过单片机IO口模拟SPI通信接口来控制16位数模转换芯片DAC8831,DAC8831根据预先输入的D/A控制字将数字信号转换成模拟电压,借助于外部运放实现双极性电压输出。实验结果表明,该系统输出电压范围为-4～+4 V、电压分辨率可达0.125 mV,低速电压扫描线性度好,具有应用灵活、外围电路简单,可靠性高的特点。     

一种基于PWM的电压输出DAC电路设计

对实际应用中的脉宽调制(PWM)波形的频谱进行了理论分析．指出通过一个低通滤波器可以把PWM调制的数模转换信号解调出来．实现从PWM到DAC的转换。论文还对转换误差产生的因素进行了分析，指出了减少误差的方法，论文给出了两种从PWM到0～5V电压输出的电路实现方法，第2种电路具有很高的转换精度。     

一种低功耗嵌入式14位400MHz数模转换器

设计了一个14位刷新频率达400MHz,用于高速频率合成器的低功耗嵌入式数模转换器。该数模转换器采用5+4+5分段式编码结构,其电流源控制开关输出驱动级采用归零编码以提高DAC动态特性。该数模转换器核采用0.18μm1P6M混合信号CMOS工艺实现,整个模块面积仅为1.1mm×0.87mm。测试结果表明,该DAC模块的微分非线性误差是-0.9～+0.5LSB,积分非线性误差是-1.4～+1.3LSB,在400MHz工作频率下,输出信号频率为80MHz时的无杂散动态范围为76.47dB,并且功耗仅为107.2mW。     

A 0.9 V 96 μW Fully Operational Digital Hearing Aid Chip

A 0.9 V 96 muW fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.     

10比特200Msps电流舵DAC的设计

实现了一款10比特200Msps采样速度的数模转换器。该数模转换器采用了8+2的分段结构,高8位比特使用温度码设计。文中详细分析了CMOS工艺下匹配问题,采取一定措施提高匹配性。该数模转换器采用3.3V供电电压,摆幅为2Vpp,提高了系统的抗干扰能力。在200Msps采样率下,后仿真结果可达到INL小于0.34LSB,DNL小于0.05LSB,有效比特数为9.9,SNDR达到61.7dB,SFDR为75.3dB。该DAC采用SMIC180nm CMOS工艺设计,整体面积为800*800μm2。     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

基于FPGA的实时光OFDM发射机的研究

基于Xilinx现场可编程门阵列(FPGA)实时产生正交频分复用(OFDM)信号,其中包括伪随机二进制序列发生器(PRBS)实现、完全并行运算反傅里叶变换(IFFT)技术的应用以及数模转换(DAC)接口电路的设计等,OFDM电信号解调后的星座图具有较好的收敛性,相应的误差矢量幅度(EVM)为4.42%。当发射机与接收端存在采样频率偏差时,各子载数据产生不同的相位旋转,系统误比特率(BER)显著升高,采样频率同步后系统性能得到明显改善。通过搭建强度调制直接检测光OFDM(O-OFDM)实验系统,传输200km标准单模光纤(SSMF)后,在接收端对O-OFDM信号进行了离线处理,与背靠背(BTB)传输相比,光功率代价小于0.6dB,实验结果表明,所设计的O-OFDM发射机具有较好的性能。     

DAC1230和单片机Atmega128接口技术研究

随着全球单片机技术的飞速发展,关于单片机及DAC芯片的应用也变得更加广泛,本文通过对DAC1230芯片与Atmega128单片机接口连接技术展开研究,目的是为了能够进一步加深对单片机及DAC芯片的结构认识,提高信号传输的可靠性,从而满足单片机市场中"高性能、低能耗"数字集成电路发展要求.