Si/SiGe PMOS器件的模拟优化设计与样品研制

通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) .     

低温制备应变硅沟道MOSFET栅介质研究

分别对300 °C下采用等离子体增强化学气相淀积(PECVD)和700 °C下采用热氧化技术制备应变硅沟道MOS器件栅介质薄膜进行了研究.采用PECVD制备SiO2栅介质技术研制的应变硅沟道PMOSFET(W/L＝20 μm/2 μm)跨导可达45 mS/mm(300 K), 阈值电压为1.2 V;在700 °C下采用干湿氧结合,制得电学性能良好的栅介质薄膜,并应用于应变硅沟道PMOSFET(W/L＝52 μm/4.5 μm)器件研制,其跨导达到20mS/mm(300 K),阈值电压为0.4 V.     

DESIGN AND FABRICATION OF Si/SiGe PMOSFETs

Based on theoretical analysis and computer-aided simulation, optimized design prin-ciples for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials, determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage.In the light of these principles, a SiGe PMOSFET is designed and fabricated successfully.Measurement indicates that the SiGe PMOSFET‘s(L=2μ同洒45 mS/mm(300K) and 92 mS/mm(77K) ,while that is 33mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

大跨导n型Si/SiGe调制掺杂场效应晶体管

报道了第一支0.25μm栅长n型Si/SiGe调制掺杂场效应晶体管的制作和器件特性结果。器件用于超高真空/化学汽相淀积(UHV/CVD)制作的器件,在300K(77K)下,应变Si沟道的迁移率和电子薄层载流子的深度为1500(9500)cm~2/V·s和2.5×10~(12)(1.5×10~(10))cm~(-2)。器件电流和跨导分别为325mA/mm和600mS/mm。这些值远优于Si MESFET,它们可与所获得的GaAs/Al-GaAs调制掺杂晶体管的结果相媲美。     

大跨导n型Si／SiGe调制掺杂场效应晶体管

报道了第一支0．25um栅长n型Si/SiGe调制掺杂场效应晶体管的制作和器件特性结果，器件用于超高真空／化学汽相淀积（UHV／CVD）制作的器件，在300K（77K）下，应变Si沟道的迁移率和电子薄层载流子的深度为1500（9500）cm2/V.s和2．5×10^12(1.5*10^10)cm^-2，器件电流和跨导分别为325mA/mm和600mS/mm，这些值远优于Si MESFET，它们可与所获得的GaAs/Al-GaAs调制掺杂晶体管的结果相媲美。     

Ga_(1-x)Al_xAs/GaAs异质结构二维电子气晶体管(TEGFET)

制备了耗尽型和增强型TEGFET,耗尽TEGFE单栅长1μm,其室温跨导g_m=90mS/mm;双栅栅长均为2μm。g_m=75mS/mm。双栅的结果优于本实验室相同结构与尺寸的离子注入型常规双栅MESFET与高掺杂沟道MIS结构肖特基势垒FET的实验结果。双栅耗尽型器件在77K下跨导增加到1.7倍。双栅增强型的TEGFET在室温0.6V栅偏压下,g_m=63mS/mm,在77K下增加到1.4倍。如器件中出现平行电导时,则器件性能退化,它不但使跨导降低,且随栅编压变化很大。文中讨论了这一现象。     

SiGe MOS器件SiO2栅介质低温制备技术研究

为了获得电学性能良好的SiGe PMOS SiO2栅介质薄膜，采用等离子增强化学汽相沉积（PECVD）工艺，对低温300℃下薄膜制备技术进行了研究。实验表明，采用适当高温、短时间对PECVD薄膜退火有助于降低薄膜中电荷密度和界面态密度。该技术用于SiGe PMOSdgrm,在300K常温和77K低温下，其跨导分别达到45mS/mm和92．5mS/mm(W/L=20μm/2μm).     

亚微米栅长调制掺杂场效应管(MODFET)的制造

本文简述了调制掺杂场效应管(MODFET)材料参数的设计原理,0.2μm栅长T型栅的制造工艺以及为了获得0.2μm栅长的器件所要求的电子束曝光的详细条件.虽然所用材料的缓冲层纯度不够高(～1×10~(15)cm~(-3)),但由于采用了T型结构,器件室温跨导值仍达到了200mS/mm,在77K为375mS/mm.     

一种适合制作CMOS的SiGePMOSFET

在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si Ge沟道的器件相当     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

SiGe pMOSFET's with gate oxide fabricated by microwave electroncyclotron resonance plasma processing

A new process, electron cyclotron resonance (ECR) microwave plasma oxidation, has been developed to produce a gate-quality oxide directly on SiGe alloys. One μm Al gate Si_0.86Ge_0.15 p-metal-oxide-semiconductor field-effect-transistors (pMOSFET's) with ECR-grown gate oxide have been fabricated. It is found that saturation transconductance increases from 48 mS/mm at 300 K to 60 mS/mm at 77 K. Low field hole mobilities of 167 cm²/V-s at 300 K and 530 cm ²/V-s at 77 K have been obtained     

High-transconductance n-type Si/SiGe modulation-doped field-effecttransistors

The authors report on the fabrication and the resultant device characteristics of the first 0.25-μm gate-length field-effect transistor based on n-type modulation-doped Si/SiGe. Prepared using ultrahigh vacuum/chemical vapor deposition (UHV/CVD), the mobility and electron sheet charge density in the strained Si channel are 1500 (9500) cm²/V-s and 2.5×10¹² (1.5×10¹² ) cm^-2 at 300 K (77 K). At 77 K, the devices have a current and transconductance of 325 mA/mm and 600 mS/mm, respectively. These values far exceed those found in Si MESFETs and are comparable to the best results achieved in GaAs/AlGaAs modulation-doped transistors     

Novel multilayer modulation doped (Al,Ga)As/GaAs structures for self-aligned gate FETs

The fabrication of self-aligned gate by ion implantation modulation doped (Al,Ga)As/GaAs field effect transistors (MODFETs) utilising a novel multilayer structure capable of withstanding the high-temperature furnace anneals required for Si implant activation is reported. Typical measured extrinsic transconductances of 175 mS/mm at 300 K and 290 mS/mm at 77 K were achieved on 1.1 ?m-gate-length devices. Values of the two-dimensional electron gas saturation velocity of 1.9×107 cm/s at 300 K and 2.7×107 cm/s at 77 K were obtained from an analysis of the FET drain current/voltage characteristics using the charge-control model.     

High-performance Si/SiGe n-type modulation-doped transistors

Enhancement-mode Si/SiGe n-type modulation-doped transistors with a 0.5-μm-length T-gate have been fabricated. Peak transconductances of 390 mS/mm at room temperature and 520 mS/mm at 77 K have been achieved. These high values are attributable to a combination of the high quality of the material used, having a room temperature mobility of 2600 cm²/V-s at an electron sheet concentration of 1.5×10¹² cm², and an optimized layer design that minimizes the parasitic series resistance and the gate-to-channel distance     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

Si/SiGe PMOSFET USING P^＋ IMPLANTATION TECHNOLOGY

Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor （PMOSFET） using P^＋ （phosphor ion） implantation technology is successfully fabricated. P^＋ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface, which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction （XRD） tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed, the sample appeared free of Threading Dislocation densities （TDs） within the SiGe layer to the limit of Transmission Electron Microscopy （TEM） analysis. Atomic Force Microscope （AFM） test of strained Si channel surface shows that Root Mean Square （RMS） is 1.1nm. The Direct Current （DC） characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.     

Enhancement of electron velocity in modulation-doped (Al,Ga)As/GaAs FETs at cryogenic temperatures

High-performance normally-off modulation-doped (Al,Ga)As/GaAs field-effect transistors with a 1 ?m gate length were fabricated and characterised. The transconductance obtained was 225 mS/mm at 300 K and 400 mS/mm at 77 K, leading to intrinsic transconductances (zero source resistance) of 305 and 565 mS/mm at 300 and 77 K, respectively. Since the device performance in short-gate transistors is limited by the electron saturation velocity, the increasing transconductance observed as the device is cooled is due to an increase in the electron velocity from about 2×107 cm/s to 3×107 cm/s. These velocities are inferred from a model developed for modulation-doped transistors and are predicted by pulse measurements in similar structures.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力