阻变存储器外围电路关键技术研究进展

阻变存储器(RRAM)是一种前景非常好的未来通用存储技术,也是当前国际学术界和工业界研究的热点。主要介绍了存储器外围电路的电路设计,并介绍了阻性存储器外围电路,包括验证电路、写电路、参考模块方案和形式、限流等关键技术的原理,重点讨论了提升复位操作速度,改善高阻值离散性,参考方案的设计和参考单元的组成,用限流实现低功耗操作的方法及其发展趋势。     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

调制型半导体激光器恒流驱动电路设计

半导体激光器驱动电流的微小变化将直接导致其输出光强的波动。为实现半导体激光器的稳定功率输出,基于电压负反馈原理设计了包含软启动和限流保护电路的恒流驱动电路;同时针对为消除背景光的影响而对光源进行调制的需要,设计了包括晶体振荡电路和分频电路的集成激光器调制电路。制作具体电路并完成了相关实验。实验结果表明该电路能够提供高稳定度的驱动电流,电流稳定度达0.05%;软启动和限流保护电路可保护半导体激光器并提高其抗冲击能力。调制电路产生半导体激光器调制所需的载波信号并直接完成输出光调制,通过开关可方便地实现从256 Hz～512 kHz范围内12种常用调制频率的选择。     

DC-10Mb/s 0.5μm CMOS激光器驱动电路的实现

设计并实现了一种适用于DC-10Mb/s速率、兼容TTL和CMOS输入电平的激光器驱动电路.该电路通过片外电阻可以独立地设置激光器发送光脉冲的‘1’功率和‘0’功率,并以闭环方式实现稳定的‘1’,‘0’发送光功率.介绍了一种新颖的峰-峰值光功率检测的工作机制,并能得到稳定的峰-峰值光功率.整个电路采用CSMC 0.5μm混合信号CMOS工艺实现,芯片最大输出驱动电流为120mA,在不要求输入码型的情况下,发送光脉冲的消光比波动在-20- ＋80℃范围内小于0.6dB.     

基于UC3863控制的LLC谐振变换器的设计及仿真

设计了一种以UC3863芯片为核心控制芯片的开关电源,其电路采用半桥结构的LLC谐振电路,带有PFC电路,且整个电路设计有自限流功能。分析了LLC谐振变换器整个电路的工作原理及自限流功能的实现。结合交流220 V输入1KW输出电路,分别对PFC电路和主电路进行仿真,仿真结果验证了该设计的可行性。     

针对深亚微米SRAM电路总剂量效应的最劣辐照表征研究

利用理论分析与试验验证手段研究了深亚微米SRAM（静态随机存取存储器）电路的最劣辐照效应。对各模块电路的辐照效应进行了详细分析：对于具备触发器结构的存储单元与运算放大器,对应的失效水平将与辐照过程中所存储状态具有极大相关性,此类电路倾向于存储或读取与辐照过程中所存储状态相同的状态值。设计了针对SRAM电路的最劣辐照测试方案,其中包含辐照后改变原有存储状态的写操作及针对改变后所存储状态进行的读操作。设计了针对容量8K位,特征尺寸0.25um的SRAM电路开展的辐照比对实验,利用该最劣辐照测试方案获取的抗总剂量水平（150krad(Si)）相对于常用的简单测试方案所获取数值（1Mrad(Si)）大大降低,说明常用的简单测试方案可能高估SRAM电路的抗辐照水平,同时验证了该最劣测试方案的合理性。     

忆阻器的建模及高精度忆阻值读写电路的设计

使用现有电路元件设计了一种荷控忆阻器的理论模型。由于把忆阻器应用于存储器、神经网络、信号处理等领域均涉及到忆阻器的读写操作,并且目前忆阻器大多是数字量0和1的操作,没有模拟量的操作。所以利用了荷控忆阻器的电荷特性,给出一种描述如何读取忆阻器的模拟忆阻值的方法。利用了荷控忆阻器的频率特性,设计了一个反馈式忆阻值写电路,该电路能够在忆阻器的阻态范围内进行任意模拟量的写操作。仿真结果验证了设计的正确性。     

基于补偿电路的SRAM读操作跟踪电路设计

在传统静态随机存储器（SRAM）读操作跟踪电路中,生产工艺和温度的偏差会直接影响到对SRAM中存储数据的正确读取。因此,在本文中,我们采用工艺拐点补偿和温度补偿的方法,设计出了新型SRAM读操作跟踪电路。所设计跟踪电路,通过在不同工艺拐点和不同温度的情况下,对时序追踪字线DBL补偿不同大小的电流,从而减小灵敏放大器输入位线电压差对工艺拐点和温度的敏感度。有效减小了工艺拐点和温度对于SRAM读操作的影响,提高了SRAM的良率。基于SMIC 40nm CMOS工艺,对上述读操作跟踪电路进行了仿真,并且分别对补偿前后进行了10000次蒙特卡罗仿真与比较,仿真结果验证了所设计电路的可靠性和有效性。     

巨磁阻生物传感器阵列及专用锁相放大器设计

EW_GⅠ是基于GMR(巨磁阻)传感器,用于检测血样中特种病毒的正在研发的生物芯片系统。叙述了其巨磁阻传感器阵列以及后端锁相放大IC电路的设计及实现。该阵列包含32个GMR传感器单元和2个传感器参考单元,形成多路的半桥式惠斯通电桥,用于感应绑定磁球的附加磁场。每个单元(100μm×100μm)由长1mm、宽7μm的巨磁电阻蜿蜒而成,该电阻采用[Ag(2nm)/NiFe(6nm)/Cu(2.2nm)/CoFe(4nm)]20结构,采用Ag作为镜面层,其饱和磁场小于等于30mT,GMR值约6%,单个传感器电阻约为780Ω。配套的锁相放大芯片包括了信号通道、参考通道、前置低噪声放大器、带通滤波器、可控增益放大器、相敏检测电路、正交移相电路、差分直流放大电路八个部分,整个设计功耗小于50mW@Vcc=3V。     

浮地频变负阻新电路与无源LC梯形滤波器的FDNR直接模拟

本文提出的浮地频变负阻新电路具有有源和无源元件少、灵敏度低、稳定性好、无需调整和易于实现等优点。它的提出,不仅解决了一般浮地频变负阻(FDNR)元件的实现问题,而且解决了直接模拟LC梯形滤波器的低灵敏度FDNR滤波器实现问题。     

基于CMI及差分电流的紫外读出集成电路的研究

本文提出了一种基于电流镜镜像积分(CMI)及差分电流结构的GaN紫外探测器读出电路结构,分析了该读出电路结构的工作原理及特点.通过SPICE对电路结构进行了仿真验证,结果显示该读出电路结构可以对探测器的光响应电流信号进行有效的读取.     

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of movingpictures

A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-μm CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access     

基于CPLD的DSP微处理器与CAN控制器接口的一种设计方法

提出了一种非多路复用总线与多路复用总线转换接口电路。以TMS320F206与SJA1000总线为例,分析了各自时序的特点,论述了两种总线转换的关键是读、写周期的使能信号和起始基准的确定,并采用复杂可编程器件CPLD实现。大量的试验验证了此接口的工作状态非常稳定。     

A new type of low power read circuit in EEPROM for UHF RFID

A novel low power read circuit without reference in 1 k-bits electrically erasable and programmable (EEPROM) for UHF RFID is designed and implemented in SMIC 0.18 μm EEPROM process. The read power consumption is optimized using a pre-charge sense amplifier. To improve the performance of the read circuit, a self-detect circuit, a read control logic and a feedback scheme are adopted, combined with a special time sequence. For a power supply voltage of 1 V, an average power consumption of 1.6 μA for the read operation of the EEPROM can be achieved when the read clock frequency is 640 kHz. What is more, with a 110 °C temperature change, the read power consumption variation is as low as 12%. The die size of the EEPROM is 0.15 mm², where the read circuit occupies 0.0125 mm².     

A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-μm effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

Development of 3T eDRAM gain cells for enhancing read margin and data retention

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz^1/2.     

Sub-1V embedded SRAM with bit-error immune dual-boosted cell technique

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 mum 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 muW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM     

A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

A 1-Mb (256 K×4) CMOS SRAM with 6-ns access time is described. The SRAM, having a cell size of 3.8 μm×7.2 μm and a die size of 6.09 mm×12.94 mm, is fabricated by using 0.5-μm triple-polysilicon and double-metal process technology. The fast access time and low power dissipation of 52 mA at 100-MHz operation are achieved by using a new NMOS source-controlled latched sense amplifier and a data-output prereset circuit. In addition, an equalizing technique at the end of the write operation is used to avoid lengthening of access time in a read cycle following a write cycle     

A full bit prefetch architecture for synchronous DRAM's

A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM is developed based on this architecture. Since the full burst read data are latched in I/O sense amplifiers by a single CAS access, a precharge operation can start as early as two clocks before the data burst cycles begin. The early precharge function allows next RAS and CAS accesses during burst reads of the previous data. With a burst length of eight, a seamless read operation is possible for any row addresses even within the same bank. The full bit prefetch architecture enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only. The SDRAM with a 1M×16-b configuration dissipates a 65-mA active current at a 100-MHz full page mode operation