Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (Zr_xSi_1−xO₂) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO₂ and ZrO₂ targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr_xSi_1−xO₂ film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr_0.85Si_0.15O₂ dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ_FE=51.7 cm²/Vs), and threshold voltage shift (ΔV_TH=0.03 V).     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases

The effects of dielectric-annealing gas (O₂, N₂ and NH₃) on the electrical characteristics of amorphous InGaZnO thin-film transistor with HfLaO gate dielectric are studied in-depth, and improvements in device performance by the dielectric annealing are observed for each gas. Among the samples, the N₂-annealed sample has a high saturation carrier mobility of 35.1 cm²/V s, the lowest subthreshold swing of 0.206 V/dec and a negligible hysteresis. On the contrary, the O₂-annealed sample shows poorer performance (e.g. saturation carrier mobility of 15.7 cm²/V s, larger threshold voltage, larger subthreshold swing of 0.231 V/dec and larger hysteresis), which is due to the decrease of electron concentration in InGaZnO associated with the filling of oxygen vacancies by oxygen atoms. Furthermore, the NH₃-annealed sample displays the lowest threshold voltage (1.95 V), which is attributed to the increased gate-oxide capacitance and introduced positive oxide charges. This sample also reveals a change in the dominant trap type due to the over-reduction of acceptor-like border and interface traps, as demonstrated by a hysteresis phenomenon in the opposite direction. Lastly, the low-frequency noise of the samples has also been studied to support the analysis based on their electrical characteristics.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

High performance electric-double-layer amorphous IGZO thin-film transistors gated with hydrated bovine serum albumin protein

Device performance of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) has been improved greatly by using bovine serum albumin (BSA) as the top gate dielectric. BSA is a natural protein with acidic and basic amino acid residues, which is easily hydrated in air ambient. A typical a-IGZO TFT with hydrated BSA as the top gate dielectric exhibits a field-effect mobility (μ_FE) value of 113.5 cm² V⁻¹ s⁻¹ in saturation regime and a threshold voltage (V_TH) value of 0.25 V in air ambient. The excellent device performance can be well explained by the formation of electric double layers (EDLs) near the interfaces of a-IGZO/hydrated BSA and hydrated BSA/gate electrode. The reliability issue of a-IGZO TFTs gated with hydrated BSA has been also investigated by using the life time test without encapsulation. The V_TH value increases and μ_FE,sat value reduces slightly for the a-IGZO TFT and remain stabilized over 60 days.     

Natural polyelectrolyte: Major ampullate spider silk for electrolyte organic field-effect transistors

The major ampullate (MA) silk collected from giant wood spiders Nephila pilipes consists of 12% glutamic acid (Glu) and 4% tyrosine (Tyr) acidic amino residues. The MA silk may act as a natural polyelectrolyte for organic field-effect transistors (OFETs). Pentacene and F₁₆CuPc OFETs were fabricated with the MA silk thin film as the gate dielectric. The MA silk thin film with surface roughness of 4 nm and surface energy of 36.1 mJ/m² was formed on glass using a hexafluoroisopropanol (HFIP) organic process. The MA silk gate dielectric in pentacene OFETs may improve the field-effect mobility (μ_FE,sat) value in the saturation regime from 0.11 in vacuum to 4.3 cm² V⁻¹ s⁻¹ in air ambient at ca. 70% RH. The corresponding threshold voltage (V_TH) value reduced from −6 V in vacuum to −0.5 V in air ambient. Similar to other polyelectrolytes, the changes of μ_FE,sat and V_TH may be explained by the generation of electric double layers (EDLs) in the MA silk thin film in air ambient due to water absorption.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Defect modification in ZnInSnO transistor with solution-processed Al2O3 dielectric by annealing

The properties of solution-processed Al₂O₃ thin films annealed at different temperatures were thoroughly studied through thermogravimetry–differential thermal analysis, UV–vis-NIR spectrophotometer measurements, scanning electron microscopy, X-ray diffraction, atomic force microscopy and a series of electrical measurements. The solution-processed ZnInSnO thin films transistors (TFTs) with the prepared Al₂O₃ dielectric were annealed at different temperatures. The TFTs annealed at 600 °C have displayed excellent electrical performance such as the field-effect mobility of 116.9 cm² V⁻¹ s⁻¹ and a subthreshold slope of 93.3 mV/dec. The performance of TFT device could be controlled by adjusting the annealing temperature. The results of two-dimensional device simulations demonstrate that the improvement of device performance are closely related with the reduction of interface defects between channel and dielectric and subgap density of stats (DOS) in the channel layer.     

Growth temperature dependence of epitaxial Gd2O3 films on Si(1 1 1)

This article reports on the epitaxy of crystalline high κ oxide Gd₂O₃ layers on Si(1 1 1) for CMOS gate application. Epitaxial Gd₂O₃ thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(1 1 1) substrates between 650 and 750 °C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7 nm for the sample deposited at the optimal temperature of 700 °C with a relatively low leakage current of 3.6 × 10^?2 A/cm² at |V_g ? V_FB| = 1 V.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V_pp differential input is improved from ?42 dB to ?55 dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of ?53 dB for 0.4V_pp differential input. It consumes 345 μw from 1.0 V single supply. Theoretical and simulated results are in good agreement.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (> 20 nm) SiO₂ gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35 nm of gate oxide can be rated at V_GS = + 12 V if one assumes continuous DC Gate-Source bias of V_GS = + 12 V at T = 175 °C for 10 years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to V_GS = + 14.7 V at T = 175 °C for the same PPM level (1 PPM). The application of the methodology for establishing the oxide thickness, t_ox, for any required voltage rating, is discussed.     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.     

Analytical long-term NBTI recovery model with slowing diffusivity and locking effect of hydrogen considered

The NBTI degradation caused by hole trapping in gate insulator process-related preexisting traps (∆ V_HT) and in generated bulk insulator traps (∆ V_OT) can recover in several seconds (< 10 s), whereas the long-term recovery is dominated by interface trap generation (∆ V_IT). In this paper, various explanations of NBTI recovery have been reviewed and a compact analytical long-term NBTI recovery model in which the slowing down diffusivity and locking effect of H₂ are involved has been derived. The triangular diffusion profile of H₂ is approximated and the fitting coefficient ξ of slowing down diffusivity is related to the stress and recovery time. Our proposed model has been validated by the previous theories and numerical calculation. Moreover, the investigation of NBTI recovery on a 40-nm CMOS process has been experimentally carried out and the results show that our compact NBTI recovery model can describe the long-term recovery well.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.