High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

An ultra low-power DAC with fixed output common mode voltage

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V_cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.     

用于CMOS图像传感器的9位10MS/s低功耗流水线ADC

提出了一个用于CMOS图像传感器的9位10MS/s、低功耗流水线ADC.为降低功耗,该设计通过采用低功耗、宽摆幅的带有增益增强结构的放大器以及将所有单元共用偏置电路的技术来实现.共用偏置技术需要仔细的版图设计和在电路中加入大的去耦合电容来实现.此外,设计中也采用电容阵列DAC来降低功耗.同时,为了增大信号处理范围,设计中还采用低阈值电压的MOS管.该ADC采用4M-1P的0.18μm CMOS工艺设计制造.对芯片的测试结果表明该设计的功耗仅为7mW,相对其他设计是相当低的.该ADC已经应用于30万像素图像传感器系统中,该系统已经流片、测试.     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

Architecture optimization for energy-efficient resolution-scalable 8–12-bit SAR ADCs

Low power analog-to-digital converters (ADCs) in energy constrained devices, such as wireless sensor readout modules, often target dynamic resolution scalability with application context to reduce the average power consumption. This work implements such an 8–12-bit resolution scalable ADC, using an oversampling and noise-shaping successive approximating register (SAR) architecture. This architecture is selected for its high power efficiency after a detailed comparison of various resolution enhancing techniques within the SAR framework. Specifically, in this paper, three resolution enhancing techniques are reviewed and compared on their energy usage namely: the majority voting, the oversampling, and the oversampling with noise shaping SAR ADC. Furthermore, the proposed resolution scalable ADC simplifies the design of the noise shaping filter by enabling the use of a first order switched-capacitor low-pass filter for shaping the comparator noise and the in-band quantization noise. The ADC design also alleviates the matching concerns by using only an 8-bit capacitive digital-to-analog converter (DAC) for a maximum 12-bit resolution, or 11-bit effective number of bits (ENOB). The architecture can be configured to allow an operation from 8-bit traditional SAR ADC up to an 11-bit ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with up to 320 kS/s and achieves a power scaling from 80 nW to 1.5 \(\upmu\)W, resulting in an steeper energy-ENOB scaling trend compared to state-of-the art resolution scalable ADCs.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

一种新型二分电容DAC的设计

为了进一步减小电容阵列DAC占用的面积,提出了一种可用于SAR ADCs的二分电容阵列(三段电容阵列,T-SC)结构。与传统二段电容阵列相比,提出的二分电容阵列在不增加对电容匹配性要求的前提下,减少了芯片面积。在理论上分析了该结构的电容失配和寄生效应,归纳提出了一种计算电容阵列DAC DNL的简易公式。Matlab仿真结果与理论分析有较好的一致性,三段电容阵列结构能够实现较好的二进制权重特性;根据提出的计算DNL的简易公式进行参数设计,仿真DNL标准偏差为0.51 LSB,与理论计算0.5 LSB相差0.01 LSB。     

一种SAR ADC电容失配自测量与数字校准技术

为了解决高分辨率逐次逼近模数转换器(SAR ADC)中,电容式数模转换器(DAC)的电容失配导致精度下降的问题,提出了一种电容失配自测量方法,以及一种可适用于各种差分电容DAC设计的低复杂度的前台数字校准方法。该方法利用自身电容阵列及比较器完成位电容失配测量,基于电容失配的转换曲线分析,对每一位输出的权重进行修正,得到实际DAC电容大小对应的正确权重,完成数字校准。数模混合电路仿真结果表明,引入电容失配的16位SAR ADC,经该方法校准后,有效位数由10.74 bit提高到15.38 bit。     

用于触摸屏控制电路的低功耗模数转换器设计

为了降低触摸屏控制电路的功耗,本文提出了一种低功耗逐次逼近型模数转换器(SAR ADC)。对该SAR ADC所采用的电容阵列数模转换器(DAC)、比较器和逐次逼近寄存器等进行了研究与设计。首先,基于两级并串耦合电容设计电容阵列DAC结构,并设计配套的参考电平转换方案。接着,设计两级全动态比较器,并分析比较器的工作原理。然后,基于动态逻辑设计低功耗低误码逐次逼近寄存器。最后,基于180nm CMOS工艺,在1V电源电压,200kHz采样频率和96.243kHz输入频率条件下对SAR ADC进行了仿真。仿真结果表明:积分非线性误差(INL)和微分非线性误差(DNL)分别为0.222/-0.203LSB和0.231/-0.184LSB,无杂散动态范围(SFDR)为76.56dB,信噪失真比(SNDR)为61.50dB,有效位(ENOB)为9.92位,功耗为0.464μW,品质因素(FOM)值为2.4fJ/Conv.-step。本文设计的低功耗SAR ADC满足触摸屏控制电路应用要求。     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

A 12-bit 10-MS/s SAR ADC with a weighted sampling time technique applied to C-DAC

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of?±?1.2LSB/?±?1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.

     

一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。     

A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS

The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous fully-differential SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. The 10-bit converter prototype has been fabricated in a standard 0.13-μm CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it’s the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm².     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.     

Adaptive successive approximation ADC for biomedical acquisition system

This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common mode voltage in order to reduce the offset voltage variation of the comparator. A test chip is implemented using a 0.18-µm CMOS process. The core area is 904×650 μm² The measurement results show that performance integrity and power efficiency are both significantly achieved in 12-bit resolution only. After the test using 1.8-V supply voltage, the SNDR is 65.59 dB and ENOB is 10.62 bits. Using 200 kS/s sampling rate, the ADC core consumption is 40.24 μW and 18.63 μW, for 12-bit and 8-bit case, respectively.     

22 μm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6 dB and a SINAD of 55 dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC׳s 0.35 μm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/−1 LSB to +1.27/−0.92 LSB, and improved the INL error from +5.35/−5.34 LSB to +3.17/−3.18 LSB. At a sampling rate of 1.1 MS/s the ADC achieved 41.5 dB SFDR, 34.2 dB SINAD, and consumed 242 μW/channel dynamic power. An individual ADC channel is only 22 μm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.