An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receivers

介绍了一种0.18μm CMOS工艺基于GSM1900(PCS1900)标准低中频接收机中的混频器.该混频器采用了一种新型的折叠式吉尔伯特单元结构.在3.3V电源电压、中频频率为100kHz的情况下,该混频器达到了6dB的转换增益,18.5dB的噪声系数(1MHz中频)和11.5dBm IIP3的高线性度,同时仅消耗7mA电流.     

一种基于0.18-μm CMOS工艺的新型超宽频带毫米波混频器设计与分析

本文提出了一种超宽频带毫米波混频器电路.混频器采用分布式拓扑结构和中频功率合成技术,具有宽带宽和高转换增益.该混频器采用TSMC 0.18-μm CMOS工艺设计并制造,芯片总面积为1.67mm².测试结果表明:混频器工作频率从8GHz到40GHz,中频频率为2.5GHz时的转换增益为-0.2dB至4dB,其本振到中频端口和射频到中频端口间的隔离度均大于50dB.整个电路的直流功耗小于32mW.     

基于倒扣技术的Ka波段环形混频器

给出了一种应用在毫米波前端的单平衡环形混频器。该混频器采用高介电常数的复合材料(R ogersDuro id3010,rε=10.2),以获得较小的芯片面积;电路设计中重点考虑了在较低的本振功率的情况下获得较小的变频损耗,并给出了一种新的混合环的分析方法。当本振在36.5 GH z有9 dBm的功率输入时,混频器有7 dB的变频损耗,双边带噪声系数11.5 dB,本振到中频和射频到中频分别有40.5 dB和31 dB的隔离度。     

一款集成驱动放大器的低变频损耗混频器设计

采用0.5μm GaAs工艺设计并制造了一款单片集成驱动放大器的低变频损耗混频器.电路主要包括混频部分、巴伦和驱动放大器3个模块.混频器的射频(RF)、本振(LO)频率为4～7 GHz,中频(IF)带宽为DC～2.5 GHz,芯片变频损耗小于7 dB,本振到射频隔离度大于35 dB,本振到中频隔离度大于27 dB.1 dB压缩点输入功率大于11 dBm,输入三阶交调点大于20 dBm.该混频器单片集成一款驱动放大器,解决了无源混频器要求大本振功率的问题,变频功能由串联二极管环实现,巴伦采用螺旋式结构,在实现超低变频损耗和良好隔离度的同时,保持了较小的芯片面积.整体芯片面积为1.1 mm×1.2 mm.     

一种使用一维电磁带隙结构的高性能Ka频段四次谐波混频器

介绍了一种全集成微带四次谐波混频器,该混频器采用了一种新型电磁带隙结构,可获得很低的变频损耗指标.阐述了一般的谐波混频理论,并用谐波平衡软件对整个电路进行优化仿真.实测得到射频在34~36GHz的频带内,固定中频为100MHz,该混频器最小变频损耗7.67dB,最大变频损耗<10dB.     

基于LTCC技术的C频段星载接收机混频器

利用低温共烧陶瓷(LowTemperature Co-fired Ceramic,简称LTCC)技术,设计制作了一种可应用于C频段星载接收机的双平衡混频器。该混频器将射频和本振巴伦等无源器件集成在多层LTCC基板内,实现了电路的小型化、高集成度和高可靠性。测试表明,当射频输入为5.925～6.425GHz、本振频率为2.225GHz、中频输出频率为3.7～4.2GHz时,混频器的变频损耗≤9.3dB,P1dB为5.7dBm,本振到射频和本振到中频的隔离度分别为39.44dB和35.58dB。混频器的尺寸为40×22×1.92mm3。     

毫米波单片有源混频器的研制

采用OMMIC 0.18μm GaAs pHEMT工艺,研制了毫米波单片有源混频器.该混频器选用单栅极单端FET混频结构.在中频输出端设计了低通滤波器,以提高LO-IF、RF-IF的隔离度.芯片的尺寸仅为0.95mm×1.85mm.在射频频率为39GHz、输出中频频率为3GHz时,该混频器的变频增益为0.6dB,LO-IF隔离度大于55dB,RF-IF的隔离度大于30dB.     

低中频接收机中高线性度正交混频器设计

本文首先以Gilbert单元为核心,利用折叠结构,设计了一种具有高线性度的CMOS单通道混频器。该混频器的输入射频信号设用了600MHz、输出中频为8MHz。接着本文应用这一混频器设计了低中频接收机中所需的双通道正交混频器。经仿真得到其在3.3V的电源电压下,转换增益为8.4dB,输入1dB压缩点和IIP3分别达到0dBm和10dBm,单边带噪声系数为16.8dB。     

基于倒扣技术的K波段 CPW环形混频器

本文给出了一种应用在汽车防撞雷达前端的单平衡环形混频器。混频器设计中采用CPW线作为传输线,以降低传输损耗,并提出了一种新的混合环的分析方法。电路设计中重点考虑了在较低的本振功率的情况下获得较小的变频损耗。当本振在25GHz有9dBm的信号功率输入时,混频器有5. 2dB的变频损耗,本振到射频和本振到中频分别有46. 4dB和37. 7dB的隔离度。该混频器的结构简单,便于批量生产。     

一种基于0.18-μm CMOS 工艺的超宽频带分布式无源栅注入混频器

本文介绍了一种基于0.18-μm CMOS 工艺的宽带无源分布式栅注入混频器。通过采用分布式拓扑结构,该混频器具有很宽的工作频带;中频输出端口使用了一个4阶低通滤波器,从而极大地提高端口之间的隔离度。此外,文中还分析了混频器的阻抗匹配与转换损耗。测试表明：该混频器在3GHz到40GHz频率范围工作时的转换损耗为 9.4 ~ 17 dB,零直流功耗,其芯片面积为0.78 mm2。在射频频率为23GHz固定中频频率为500MHz时的输入参考1dB压缩点大于4dBm。在整个工作频带内,其射频到本振端口、射频到中频端口及本振到中频端口的隔离度分别大于21dB, 38dB,45dB。该混频器适用于WLAN,UWB,Wi-Max,车载雷达系统和其它毫米波射频的相关应用。     

CMOS multiband low-noise amplifier using inner diameter shared inductors

A new integrated inductor structure suitable for multiband application is proposed and used to implement a CMOS multiband low-noise amplifier. Its occupied silicon area can be decreased by more than 40% while its performance is almost the same as those of LNAs using the conventional inductor structure. It is fabricated in a 0.13 mm CMOS process and its measured results show gains of 16.8, 15.8 and 15.5 dB, with NFs of 1.4, 1.8 and 1.9 dB, and IIP3 of 4, 0 and 22 dBm for the 850, 1800/1900 and 2100 MHz bands, respectively.     

1.9GHz高线性度上混频器设计

介绍了采用0.35μm CMOS工艺实现的单边带上变频混频电路。该混频电路可用于低中频直接混频的PCS1900(1 850~1 910 MHz)发射器系统中。电路采用了multi-tanh线性化技术,可以得到较高的线性度。在单电源+3.3 V下,上混频器电流约为6 mA。从上混频电路输出级测得IIP3约8 dBm,IP1dB压缩点约为0 dBm。     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

一种小型的手机平面倒F天线

设计了一个可工作在GSM850/DCS1800/PCS1900这3个频段的小型加载寄生单元平面倒F天线。天线在820～903 MHz,1.69～2.12 GHz频率范围内的回波损耗可达到-5 dB以下,在850 MHz,1800 MHz,1 900 MHz频率处天线最大增益的测量值分别为3.08 dB,4.41 dB,3.40 dB,满足移动终端在GSM850/DCS1800/PCS1900这3个频段的使用要求。该天线尺寸小、重量轻,适用于移动通信终端。     

Broadband amplification in CMOS technology using cascadedsingle-stage distributed amplifier

Feasibility of the cascaded single-stage distributed amplifier (CSDA) for ultra broadband amplification in complementary metal-oxide-semiconductor (CMOS) technology is investigated. A number of unique benefits gained from the CMOS CSDA over the conventional CMOS distributed amplifier structure are highlighted along with bandwidth analysis and helpful consideration. Simulated in the standard digital 0.35 μm CMOS process with realistic parasitic models, a prototype design of a four-stage CMOS CSDA provides 21 dB power gain at 5 GHz bandwidth, better than -10 dB input/output return loss and dissipates < 132 mW     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A 28GHz CMOS FREQUENCY DOUBLER WITH TFMS

In this paper, a 28GHz CMOS frequency doubler with TFMS (thin film microstrip line) has been introduced in order to experimentally study the possibility of millimeter wave CMOS devices based on TFMS. The present doubler shows 2dB conversion loss and approximately 12dB suppression to fundamental frequency. The result shows that the CMOS technology compatible TFMS are promising on the design of millimeter-wave CMOS devices.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Design of a wide-band frequency synthesizer based on TDC and DVC techniques

A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the capabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6-/spl mu/m CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can improve about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with <22 kHz resolution at 3.3 V. Simulation and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time.