A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

采用PSO算法的S波段EDFA的优化设计

成功地使用粒子群优化(PSO)算法优化设计了多级S波段EDFA,仿真结果表明,输入信号功率为-20 dBm时在1486～1520 nm可实现平坦增益,两级泵浦总功率为380 mW,平均增益可达10 dB以上,增益平坦度小于0.1 dB,噪声系数小于5 dB,满足WDM/DWDM系统的需求.另外,还重点对插入长波长ASE...     

具有片上数字控制频率调谐的9MHz有源RC滤波器

讨论了适用于无线局域网零中频收信机的4阶切比雪夫有源RC滤波器,为消除工艺偏差和环境变化对截止频率的影响,提出片上数字控制频率调谐电路.采用TSMC-0.25μm 1P5M CMOS工艺进行制造,测得调谐锁定时,滤波器的截止频率为9MHz,通带增益为0dB,增益波动小于1dB,带外抑制在30MHz处小于-40dB,通带内噪声小于-142dBm/Hz,当两输入信号的功率为-10dBm时,三阶交调小于-70dBm.     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

一个950MHz CMOS低噪声放大器的设计

介绍了一个采用0.18μm 1.8V RF CMOS工艺,适合GSM接收器,中心频率为950MHz的低噪声放大器(LNA)的设计过程,并给出了spectreRF的模拟结果.在935～960MHz频带内,LNA功率增益大于16dB,阻抗匹配系数S11小于-18dB,噪声系数(NF)小于2.7dB,IIP3为-3.06dBm,ldB压缩点为-10.955dBm,功耗小于20mW.     

具有片上数字控制频率调谐的9MHz有源RC滤波器

讨论了适用于无线局域网零中频收信机的4阶切比雪夫有源RC滤波器,为消除工艺偏差和环境变化对截止频率的影响,提出片上数字控制频率调谐电路．采用TSMC 0.25μm 1P5M CMOS工艺进行制造,测得调谐锁定时,滤波器的截止频率为9MHz,通带增益为0dB,增益波动小于1dB,带外抑制在30MHz处小于－40dB,通带内噪声小于－142dBm/Hz,当两输入信号的功率为－10dBm时,三阶交调小于－70dBm．     

一种宽带接收射频前端设计与实现

本文设计了一种超外差架构的超宽带接收射频前端,工作频段覆盖400MHz~2000MHz,接收增益50dB,噪声系数小于6dB,中频输出频率70MHz,输出1dB压缩点大于18dBm,输出三阶交调节点大于30dBm,瞬时态范围大于55dB,测试结果和仿真结果基本一致,符合设计预期.     

基于InGaP/GaAs HBT的X波段MMIC功率放大器研制

研制了X波段的InGaP/GaAs HBT单级MMIC功率放大器,该电路采用自行开发的GaAs HBT自对准工艺技术制作.电路偏置于AB类,小信号S参数测试在8～8.5GHz范围内,线性增益为8～9dB,输入驻波比小于2,输出驻波比小于3,优化集电极偏置后,线性增益为9～10dB.在8.5GHz进行连续波功率测试,在优化的负载阻抗条件下,P1dB输出功率为29.4dBm,相应增益7.2dB,相应PAE〉40%,电路的饱和输出功率Psat为30dBm.     

基于InGaP/GaAs HBT的X波段MMIC功率放大器研制

研制了X波段的InGaP/GaAs HBT 单级MMIC功率放大器,该电路采用自行开发的GaAs HBT自对准工艺技术制作.电路偏置于AB类,小信号S参数测试在8～8.5GHz范围内,线性增益为8～9dB,输入驻波比小于2,输出驻波比小于3,优化集电极偏置后,线性增益为9～10dB.在8.5GHz进行连续波功率测试,在优化的负载阻抗条件下,P1dB输出功率为29.4dBm,相应增益7.2dB,相应PAE＞40%,电路的饱和输出功率Psat为30dBm.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier(LNA) with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.     

A 2.5-GHz BiCMOS transceiver for wireless LAN's

A BiCMOS transceiver intended for spread spectrum applications in the 2.4-2.5 GHz band is described. The IC contains a low-noise amplifier (LNA) with 14 dB gain and 2.2 dB NF in its high-gain mode, a downconversion mixer with 8 dB gain and 11 dB NF, and an upconversion mixer with 17 dB gain and P_{-1 dB} of +3 dBm out. An on-chip local oscillator (LO) buffer accepts LO drive of -10 dBm with a half-frequency option allowed by an on-chip frequency doubler. Power consumption from a single 3-V supply is 34 mA in transmit mode, 21 mA in receive mode, and 1 μA in sleep mode     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

5~22GHz平坦高增益单片低噪声放大器

使用0.25μm G aA s PHEM T工艺技术,设计和制造了性能优良的5-22 GH z两级并联反馈单片低噪声放大器。在工作频率5-22 GH z内,测得增益G≥18 dB,带内增益波动ΔG≤±0.35 dB,噪声系数N F≤3.2 dB,输入输出驻波V SW R≤1.7,最小分贝压缩点输出功率P1dB≥10.5 dBm,电流增益效率达2.77 mA/dB。测试结果验证了设计的正确性。     

CMOS宽带线性可变增益低噪声放大器设计

文章设计了一种48MHz~860MHz宽带线性可变增益低噪声放大器,该放大器采用信号相加式结构电路、控制信号转换电路和电压并联负反馈技术实现。详细分析了线性增益控制、输入宽带匹配和噪声优化方法。采用TSMC0.18μm RF CMOS工艺对电路进行设计,仿真结果表明,对数增益线性变化范围为-5dB~18dB,最小噪声系数为2.9dB,S11和S22小于-10dB,输入1dB压缩点大于-14.5dBm,在1.8V电源电压下,功耗为45mW。     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

一种应用于GPS接收机的全单片CMOS低噪声放大器

采用0.18μm1.8V mixed CMOS工艺设计并实现了一种应用于GPS接收机的CMOS低噪声放大器,采用片内螺旋电感实现输入匹配和单片集成。测试结果表明在1.575GHz时,工作电流8mA,增益20dB,噪声系数小于1.7dB,IIP3为-10dBm。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。