1 V 2 GHz CMOS frequency divider

A new frequency divider, called differential injection locking, is proposed. The proposed divider has no transistor stacking to suppress the performance degradation due to supply voltage reduction. It is shown that the proposed frequency divider achieves 2 GHz with 1 V supply voltage and 540 /spl mu/W power consumption.     

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

1 V 10 GHz CMOS frequency divider with low power consumption

A low supply voltage and low power ultra-high frequency divider is investigated. The proposed inverter of the frequency divider is able to operate at higher frequencies with enhanced output voltage swing and lower power consumption under an ultra-low supply voltage compared to that of existing divide-by-2 units. The frequency divider implemented with this inverter using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 10 GHz for a 1 V supply voltage with 1.3 mW power consumption.     

Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range

A 0.8-V CMOS coupling current-mode injection-locked frequency divider (CCMILFD) with 19.5% locking range and a current-injection current-mode logic (CICML) frequency divider have been designed and fabricated using 0.13-$mu{hbox{m}}$ 1p8m CMOS technology. In the proposed CCMILFD, the current-mode technique to minimize the loss of input signals and the coupling circuit to enlarge the phase response have been designed to increase the locking range. The locking range of the fabricated CCMILFD is 4.1 GHz with a power consumption of 1.51 mW from a power supply of 0.8 V. In the proposed CICML frequency divider, the current-injection interface is applied to the current inputs to make the circuit operated at a higher frequency with low power consumption under a low voltage supply. The operation frequency of the fabricated CICML frequency divider can divide the frequency range from CCMILFD and consume 1.89 mW from a 0.8-V voltage supply. The chip core areas of the CCMILFD and CICML frequency divider without pads are 0.23 and 0.015 $ {hbox{mm}}^{2}$, respectively. The proposed circuits can be operated in a low supply voltage with the advantages of a wider locking range, a higher operation frequency, and lower power consumption.      

A 15-GHz broad-band /spl divide/2 frequency divider in 0.13-/spl mu/m CMOS for quadrature generation

This letter presents a 0.13-/spl mu/m CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of the loop gain phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15GHz, featuring a 31% locking range. The divider dissipates 3mA from a 1.2-V power supply.     

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-/spl mu/m SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6/spl plusmn/ 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage.     

Design of a low power wide-band high resolution programmable frequency divider

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.     

96-GHz static frequency divider in SiGe bipolar technology

A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).     

Sub-1 V Low Power Wide Range Injection-Locked Frequency Divider

In this letter, the sub-1 V low power, wide range operation of an injection-locked frequency divider with a common-gate configuration is presented. The performances in terms of locking range and power consumption have been improved in the sub-1 V low supply voltage. Two set of prototypes, performing divide-by-2 and divide-by-3, have been fabricated in CSM 0.18 mum CMOS process to verify the proposed designs. In the proposed units, a locking range of 40% has been achieved with a power consumption of 0.24 mW in the 0.8 V supply voltage. The operating range of 2.2 GHz to 5.2 GHz has been achieved with a power consumption of 1.1 mW for a 1.5 V supply voltage.     

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-/spl mu/m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.     

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.     

Colpitts Injection-Locked Frequency Divider Implemented With a 3-D Helical Transformer

This letter proposes a wide locking range and low power complementary Colpitts injection-locked frequency divider (ILFD) employing a 3-D helical transformer. The proposed ILFD consists of two single-ended complementary Colpitts oscillators coupled by a 3-D transformer to form a differential oscillator. The aim of using the 3-D transformer is to reduce chip size. The divide-by-2 LC-tank ILFD is implemented by adding an injection nMOS between the differential outputs of the voltage controlled oscillator. The measurement results show that at the supply voltage of 1.8 V, the divider free-running frequency is tunable from 4.24 to 4.8 GHz. At the incident power of 0 dBm, vtune=0.9 V, and V _DD=1.5 V, the locking range is about 2.4 GHz (26.9%), from the incident frequency 7.7 to 10.1 GHz. The core power consumption is 3.9 mW. The die area is 0.548times 0.656 mm².     

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.     

A 3 mW 54.6 GHz Divide-by-3 Injection Locked Frequency Divider With Resistive Harmonic Enhancement

A 54.6 GHz divide-by-3 injection locked frequency divider with low power consumption is presented. A resistive feedback is implemented to achieve a stable dc input and higher injection efficiency. Compared with the conventional design, it exhibits a better supply voltage rejection and wider locking range while a small silicon area is maintained. Fabricated in a TSMC 65 nm bulk CMOS process, this divider operates from 48.8 to 54.6 GHz and consumes 3 mW from a 0.9 V supply.      

A K-band down-conversion mixer with 1.4-GHz bandwidth in 0.13-/spl mu/m CMOS technology

A low power and low voltage down conversion mixer working at K-band is designed and fabricated in a 0.13/spl mu/m CMOS logic process. The mixer down converts RF signals from 19GHz to 2.7GHz intermediate frequency. The mixer achieves a conversion gain of 1dB, a very low single side band noise figure of 9dB and third order intermodulation point of -2dBm, while consuming 6.9mW power from a 1.2V supply. The 3-dB conversion gain bandwidth is 1.4GHz, which is almost 50% of the IF. This mixer with small frequency re-tuning can be used for ultra-wide band radars operating in the 22-29GHz band.     

A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.     

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz     

V-band harmonic injection-locked frequency divider using cross-coupled FETs

A V-band 1/2 frequency divider is developed using harmonic injection-locked oscillator. The cross-coupled field effect transistors (FETs) and low quality-factor microstrip resonator are employed as a wide-band oscillator to extend the locking bandwidth. The second harmonic of free-running oscillation signal is injected to the gates of cross-coupled FETs for high-sensitivity superharmonic injection locking. The fabricated microwave monolithic integrated circuit frequency divider using 0.15-/spl mu/m GaAs pHEMT process showed a maximum locking range of 7.4 GHz (from 65.1 to 72.5 GHz) under a low power dissipation of 100 mW. The maximum single-ended output power was as high as -3 dBm.     

A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider

A high-frequency CMOS injection-locked frequency divider (ILFD) is presented by using the distributed LC, series inductor peaking, and multiple-injection techniques. The theoretical analysis for the aforementioned techniques will be given. This ILFD has been fabricated in a 65-nm CMOS process. The core area is 0.4 mm times 0.36 mm without pads. The measured locking range is from 104 to 112.8 GHz, and its power consumption is 7.2 mW from a supply of 1.2 V.     

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.