Weak inversion charge injection in analog MOS switches

The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor     

An experimental study of the BO-MOS dynamic RAM cell

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N⁺diffusion. This three-dimensional structure results in a cell size of6F^{2}with a minimum feature sizeFand the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented withF = 4-µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.     

A model for analyzing the interface properties of asemiconductor-insulator-semiconductor structure. I. Capacitance andconductance techniques

A model is presented for analyzing the interface properties of a semiconductor-insulator-semiconductor (SIS) capacitor structure. By introducing a coupling factor, conventional metal-oxide-semiconductor (MOS) capacitor theory is extended to analyze the interface properties of the film/buried-oxide/substrate interfaces of a silicon-on-insulator (SOI) material. This model was used to determine parameters such as doping concentration, buried oxide thickness, fixed oxide charge, and interface trap density from the SIMOX (separation by implantation of oxygen) based SIS capacitors     

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage (C-V) characteristics of these devices.Techniques are presented for determining the impurity profile of the buried layer from the low frequency C-V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C-t) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.     

Surface charges and surface potential in silicon surface inversion layers

The effect of interface charges on the channel conductance in MOS transistors has been investigated. It has been found that, by measuring the conductance as a function of temperature, it is possible to determine both the "fixed" interface charge which is independent of the surface potential and the charge trapped in surface states whose occupancy is a function of the surface potential. The characteristics of the two charge components are discussed. It appears that neither a continuous nor a delta-function energy distribution alone is adequate to describe the observed surface-state density.     

Electrical characterization of dielectrically isolated siliconsubstrates containing buried metallic layers

Dielectrically isolated substrates containing buried highly conducting WSi₂ layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 μm thick with a buried WSi₂ layer adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 μs were measured indicating the suitability of these substrates for use in device manufacture     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are described. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are descried. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation

MOSFET capacitor models implemented in circuit simulators currently do not guarantee charge conservation, which is extremely crucial for the simulation of dynamic RAM's, switched capacitor filters, and other MOS VLSI circuits. Several MOSFET capacitor models have been introduced in the literature; however, none of these models addresses the actual reasons of charge nonconservation in SPICE2. This charge conservation problem has been studied and the causes are found. Our investigations show that charge is the appropriate state variable, and that the nonconservation of charge in SPICE2 stems from a numerical integration problem quite independent of the device physics. A new charge model has been derived, implemented in SPICE2, and tested. The new model differs from the previous models in two respects. First, it uses both charge equations and capacitance equations. Second, the partitioning of the channel charge between the source and drain terminals is carried out by requiring the charge equations to satisfy self-consistent boundary conditions. A strong emphasis is placed on charge continuity, both in the conventional operating region and in the region of weak inversion and accumulation. Benchmark tests indicate that this new model conserves charge while reducing the simulation time by 18-85 percent compared to Meyer's model which was originally used in SPICE2.     

Simulation of substrate hot-electron injection

Electron trapping in thin oxide and interface state generation has been investigated using a constant-current stressing technique. Assuming finite-temperature Fowler-Nordheim tunneling, semiempirical simulations of voltage versus stress time behavior were obtained for an MOS diode. A trapped charge model was used to simulate voltage versus stress-time behavior. The comparison between measurement and simulation results yields information about trapped charges in the oxide and at the oxide-substrate interface. The model can serve as the basis for improved understanding of the more complex phenomenon of channel hot-carrier injection in MOS transistors     

A new method for fixed oxide charge determination using a dual-gateMOS capacitor

A new method for fixed oxide charge determination at the silicon-silicon-dioxide interface is presented. It is based on high-frequency C-V measurements of a dual-gate MOS capacitor. Using this technique the fixed oxide charge can be accurately without knowledge of the work-function difference by means of one simple measurement. Due to its simplicity and ease of automation it can be applied to characterization and process optimization of MOS technology     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm²cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.     

Accurate modeling of the effects of fringing area interface traps on scanning capacitance microscopy measurement

Scanning capacitance microscopy (SCM) is a dopant profile extraction tool with nanometer spatial resolution. While it is based on the high-frequency MOS capacitor theory, there are crucial second-order effects which make the extraction of dopant profile from SCM data a challenging task. Due to the small size of the SCM probe, the trapped charges in the interface traps at the oxide-silicon dioxide interface surrounding the probe significantly affect the measured SCM data through the fringing electric field created by the trapped charges. In this paper, we present numerical simulation results to investigate the nature of SCM dC/dV data in the presence of interface traps. The simulation takes into consideration the traps' response to the ac signal used to measure dC/dV as well as the fringing field of the trapped charge surrounding the probe tip. In this paper, we present an error estimation of experimental SCM dopant concentration extraction when the interface traps and fringing field are ignored. The trap distribution in a typical SCM sample is also investigated.     

适合低功耗工作的MOS电荷泵

提出了两种适合在低功耗条件下工作的电荷泵电路,预充电电荷泵采用预充电机制提高了电荷泵的工作效率;而Domino电荷泵则采用内部电路控制电荷泵充电电容的充放电,不仅降低了功耗,同时均化了瞬态功耗.这解决了电荷泵在充电期间功耗过大的问题,使它们不仅能适用于有较强电源的电路,也可以在无源或低功耗的环境下工作.     

A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Numerical analysis of MOS magnetic field sensors

A new method of numerical analysis of MOS magnetic field sensors is described, which is based on a lumped discrete approach and the application of a general-purpose circuit-analysis program. The channel region of the device is represented by a network of identical L-type circuit cells. A cell consists exclusively of conventional MOS devices, independent voltage sources and controlled current sources, while the magnetic field appears as a parameter in some of these devices. The method allows for an accurate two-dimensional numerical analysis of MOS sensors, including effects which have been neglected hitherto, such as transverse current flow and nonuniform charge density across the channel. Numerical results are given for conventional MOS plates, split-drain MOS devices and distributed current source biased MOS Hall plates.     

A new quantitative model for weak inversion charge injection inMOSFET analog switches

This paper proposes a new model concerning the channel charges in weak inversion injected from a turn-off MOSFET into a holding capacitor. This portion of charge injection has recently been newly observed, showing a significant contribution to the switch-induced error voltage on the switched capacitor. Our model is derived at the critical point where the device is operated in the transition region between strong inversion and weak inversion. This point has been expressed explicitly as a function of the DC input voltage, the threshold voltage, and the fall time of the gate voltage. The ability of the model in accurately determining quantitatively the impact of the weak inversion charge injection on the error voltage has been extensively judged experimentally and by two-dimensional mixed-mode simulation for a wide variety of design parameters such as the channel width and length, the holding capacitance, the fall time of the gate voltage, and the DC input voltage The assumptions utilized in the model development have also been validated