FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.     

An On-Chip BP Learning Neural Network with Ideal Neuron Characteristics and Learning Rate Adaptation

An on-chip BP(Back-Propagation) learning neural network with ideal neuron characteristics and learning rate adaptation is designed. A prototype LSI has been fabricated with a 1.2 m CMOS double-poly double-metal technology. A novel neuron circuit with ideal characteristics and programmable parameters is proposed. It can generate not only the sigmoid function but also its derivative. The test results of this neuron circuit show that both functions match with their ideal values very accurately. A learning rate adaptation circuit is also presented to accelerate the convergence speed. The 2-D binary classification and sin(x) function fitness experiments are done to the chip. Both experiments verify the superior performance of this BP neural network with on-chip learning.     

采用遗传算法的一种可重构ANN的电路设计

提出了一种新型的sigmoid函数发生器.它不仅简单、快速，与理想sigmoid函数的拟合程度好，而且可实现阈值和增益因子的编程，因而有很大的应用范围和良好的应用前景.设计了神经元以及Gilbert乘法器、数字存储器、D/A转换器等神经网络的基本单元.说明了遗传算法（GA）作为人工神经网络（ANN）学习算法的有利因素.利用上述电路，采用GA，设计了可重构ANN.对各单元电路和整个ANN都用标准1.2μm CMOS工艺的第47级模型进行了HSPICE模拟.结果表明它们的功能正确、性能优良.     

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative

In this brief, we present a new circuit technique to generate the sigmoid neuron activation function (NAF) and its derivative (DNAF). The circuit makes use of transistor asymmetry in cross-coupled differential pair to obtain the derivative. The asymmetry is introduced through external control signal, as and when required. This results in the efficient utilization of the hardware by realizing NAF and DNAF using the same building blocks. The operation of the circuit is presented in the subthreshold region for ultra low-power applications. The proposed circuit has been experimentally prototyped and characterized as a proof of concept on the 1.5-/spl mu/m AMI technology.     

An expandable on-chip BP learning neural network chip

An expandable on-chip back-propagation (BP) learning neural network chip is designed. The chip has four neurons and 16 synapses. Large-scale neural networks with arbitrary layers and discretional neurons per layer can be constructed by combining a certain number of such unit chips. A novel neuron circuit with programmable parameters, which generates not only the sigmoid function but also its derivative, is proposed. The neuron has a push-pull output stage to gain strong driving ability in both charge and discharge processes, which is very important in heavy load situations. An improved version of the Gilbert multiplier is also proposed. It has large linear range and accurate zero point. The chip is fabricated with a standard 0.5 μm CMOS, double-poly, double-metal technology. The results of parity experiments demonstrate its ability of on-chip BP learning.     

Dynamic MOS sigmoid array folding analog-to-digital conversion

A dynamic, saturating difference circuit for large-scale parallel folding analog-to-digital conversion is presented. The circuit comprises a subthreshold nMOS transistor source-coupled to a capacitor, implementing a log-domain integrator. The output current is a logistic sigmoidal function of the change in voltage on the gate. Offset and gain of the differential sigmoid are controlled by timing of global clock signals and are independent of transistor mismatch. Folding operation for analog-to-digital conversion is obtained by differentially combining and integrating currents from a bank of sigmoid units. A 128-channel parallel bank of 4-bit Gray-code folding analog-to-digital converters measures 0.75 mm/spl times/2 mm in 0.5 /spl mu/m CMOS and delivers 768 Msps at 82-mW power dissipation.     

一种学习速率自适应的可编程片上学习BP神经网络电路系统的设计

设计了一种学习速率自适应的可编程片上学习BP神经网络电路系统.整个系统由前向网络、误差反传网络两部分组成.提出了一种新型的可编程S型函数及其导数的发生器电路.它不仅产生S型函数,完成非线性I－V转换;还利用前向差分法,产生S型函数的导数.这两种函数不仅与理想函数的拟合程度很好,而且易实现对阈值和增益因子的编程.为提高BP神经网络片上学习的收敛速度,还提出了学习速率自适应电路.本文采用标准1.2μm CMOS工艺的模型参数,对整个系统进行了sin(x)函数拟合等模拟实验,验证了该片上学习BP神经网络的优越性能.     

Back-Gate Effect to Generate Derivative of Neuron Activation Function

A simple neuron circuit is presented which can generate the sigmoid neuron activiation function (NAF) and its derivative (DNAF) by introducing asymmetric body biasing in the cross-coupled differential pair. The mode of operation is controlled externally. This results in the efficient utilization of the hardware by realizing NAF and DNAF using the same building blocks. The circuit is prototyped and characterized as a proof of concept on 1.5 m AMI technology.     

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0-μm double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock     

零中频DVB/DAB/CMMB调谐器中可编程信道滤波器设计

介绍了应用于多模多频(DVB/DAB/CMMB)移动数字电视接收的可编程信道滤波器设计.滤波器采用0.1dB波纹的7阶切比雪夫(Chebyshev)Ⅰ型低通结构,截止频率1.8/2.5/3/3.5/4 MHz可编程,在偏离截止频率1.25/4 MHz的频点上,分别实现26/57 dB衰减.多级直流负反馈环路用于抵消因版...     

一种新颖的可编程电压监测芯片

提出了一种新颖的可编程电压监测芯片设计。该芯片无需任何外部元件,仅对3个编程管脚采取不同的连接方式,即可实现36种不同的编程状态,一颗芯片可以覆盖1.5V到5.0V的电压范围。同时,特殊时序的采样保持电路和数字限流模块的设计使其具有极低的静态功耗。该芯片基于0.5μm的混合信号工艺实现,芯片面积为0.24mm2,仅消耗3μA静态电流。     

Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

Digital design of sigmoid approximator for artificial neuralnetworks

A digital design for piecewise-linear (PWL) approximation to the sigmoid function is presented. Circuit operation is based on a recursive algorithm that uses lattice operators max and min to approximating nonlinear functions. The resulting hardware is programmable, allowing for the control of the delay-time/approximation-accuracy rate     

An Elevator Speed-Control System Using Squirrel-Cage Induction Motors

An electronic control system with speed feedback to achieve excellent riding comfort and accurate floor-levelling in medium-speed elevators driven by squirrel-cage induction motors is described. Stepless control of both acceleration and deceleration of the elevator car is obtained, employing only two thyristors and two diodes in the power control circuit. Accurate floor levelling and smooth deceleration are achieved using a novel digital speed-reference circuit which uses programmable memory to generate the speed pattern directly as a function of the position of the elevator car. The system described is simpler, lower in cost, and easier to maintain compared to dc motor-driven elevators of the same performance for car speeds up to 2 m/s.     

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.     

A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-/spl mu/m CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.     

A spread-spectrum clock generator with triangular modulation

In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS single-poly quadruple-metal process. The proposed SSCG can generate clocks of 66, 133, and 266 MHz with center spread ratios of 0.5%, 1%, 1.5%, 2%, and 2.5%. Experimental results confirm the theoretical analyses.     

基于PLD的m序列发生器

ＰＬＤ器件加上软件开发系统，可在计算机上完成各种数字逻辑电路系统的分析和设计，本文介绍了ＰＬＤ器件用于ｍ序列发生器的设计，给出了基于ＰＬＤ的数字逻辑电路系统的计算机辅助分析和设计方法。     

FDP FPGA芯片的设计实现

研究了新型的FDP FPGA电路结构及其设计实现.新颖的基于3输入查找表的可编程单元结构,与传统的基于4输入查找表相比,可以提高约11%的逻辑利用率;独特的层次化的分段可编程互联结构以及高效的开关盒设计,使得不同的互联资源可以快速直接相连,大大提高了可编程布线资源效率.FDP芯片包括1600个可编程逻辑单元、160个可用IO、内嵌16k双开块RAM,采用SMIC 0.18μm CMOS工艺全定制方法设计并流片,其裸芯片面积为6.104mm×6.620mm.最终芯片软硬件测试结果表明:芯片各种可编程资源可以高效地配合其软件正确实现用户电路功能.