SAR图像CFAR检测的快速算法综述

针对合成孔径雷达(Synthetic aperture radar, SAR)图像目标检测中恒虚警率(Constant false alarm rate, CFAR)算法的广泛应用, 进行CFAR检测的快速算法分析具有重要研究价值. 首先概述了当前国内外对SAR图像CFAR检测快速算法的研究现状; 然后分别从快速预筛选和迭代计算方法两个方面对各类快速算法的实时性及性能进行了分析总结, 给出了四种基本CFAR检测器的迭代计算公式, 并提出了一种研究CFAR检测快速算法的基本框架, 现有的快速算法均可纳入该理论框架予以分析; 最后, 以经典双参数CFAR检测算法为例, 对该基本框架进行仿真实现和性能分析, 验证了其可行性与检测性能．结果表明: 新的CFAR检测快速算法基本框架充分融合了快速预筛选思想和迭代计算方法的优势, 有效提高了CFAR算法在SAR图像检测应用中的执行效率.     

An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP

Digital Pulse-Doppler radar chain consists of signal processing algorithms that require high computing power. Multi-processor and multi-core parallel embedded machines are one of the solutions to meet real-time constraints of many radar applications. In this paper, we proposed efficient and scalable parallelization methods of the Pulse-Doppler radar signal processing chain. First, we evaluated Open Multi Processing (OpenMP) to identify its best scheduling technique in order to exploit efficiently the available computing cores. Then, we have proposed new parallel and scalable approaches based on direct memory access (DMA) and inter-processor communication (IPC) techniques, combined with the best OpenMP scheduling method to accelerate radar signal processing chain. To prove the scalability of our proposed parallel approaches, two radar use cases with different real-time and memory constraints have been experienced. We used the eight cores C6678 digital signal processor (DSP) as a target for all our implementations. The obtained results show an overall parallel efficiency of 95%, which is better than the best state-of-the-art implementations.     

Constant false alarm rate detector based on the maximal reference cell

In order to improve the detection performance of constant false alarm rate (CFAR) detectors in multiple targets situations, a CFAR detector based on the maximal reference cell (MRC) named MRC-CFAR is proposed. In MRC-CFAR, a comparison threshold is generated by multiplying the amplitude of MRC by a scaling factor. The number of the reference cells left, whose amplitudes are smaller than the comparison threshold, is counted and compared with a threshold integer. Based on the comparison result, proper reference cells are selected for detection threshold computation. A closed-form analysis for MRC-CFAR in both homogeneous and non-homogeneous environments is presented. The performance of MRC-CFAR is evaluated and compared with other CFAR detectors. MRC-CFAR exhibits a very low CFAR loss in a homogeneous environment and performs robustly during clutter power transitions. In multiple targets situations, MRC-CFAR achieves a much better detection performance than switching CFAR (S-CFAR) and order-statistic CFAR (OS-CFAR). Experiment results from an X-band linear frequency modulated continuous wave radar system are given to demonstrate the efficiency of MRC-CFAR. Because ranking reference cells is not required for MRC-CFAR, the computation load of MRC-CFAR is low; it is easy to implement the detector in radar system in practice.     

一种脉冲多普勒雷达数字信号处理机的设计

针对某型脉冲对多普勒雷达的信号处理要求,设计了一种全数字化信号处理机。该信号处理机采用"ADC+FPGA+DSP+存储器"结构,具有体积小、重量轻、功耗低、可靠性高等优点。重点讨论了信号处理中数据采集、脉冲积累及目标检测的方法和实现。     

基于ADSP21160的目标检测算法实现

强杂波背景中的雷达目标恒虚警检测是雷达信号处理的重要组成部分。本文首先介绍了数字信号处理芯片ADSP21160的主要特点，然后讨论了瑞利分布杂波背景中雷达目标恒虚警检测的原理，最后着重阐述了基于数字信号处理芯片ADSP21160实现杂波背景中雷达目标恒虚警检测的方法和仿真实验结果。     

Matrix CFAR detectors based on symmetrized Kullback–Leibler and total Kullback–Leibler divergences

Target detection in clutter is a fundamental problem in radar signal processing. When the received radar signal contains only few pulses, it is difficult to achieve a satisfactory performance using the traditional detection algorithm. In recent times, a generalized constant false alarm rate (CFAR) detector on the Riemannian manifold of Hermitian positive-definite (HPD) matrix was proposed. The employment of this detector, which compares the Riemannian distance between the covariance matrix of the cell under test (CUT) and an average matrix of reference cells with a given threshold, has significantly improved the detection performance. However, the application of this detector in real scenarios is still limited by two problems; it is computationally expensive and the detection performance is not very good since the Riemannian distance is utilized. In this paper, the symmetrized Kullback–Leibler (sKL) and the total Kullback–Leibler (tKL) divergences, instead of the Riemannian distance, are used as dissimilarity measures in the matrix CFAR detector. According to sKL and tKL divergences, three average matrices, the sKL mean, the sKL median, and the tKL t center, are derived. Furthermore, the relationship between the detection performance and the anisotropy of the distance measure used in the matrix CFAR detector is explored. Numerical experiments and real radar sea clutter data are given to confirm the superiority of the proposed algorithms in terms of the computational complexity and the detection performance.     

一种自适应的合成孔径雷达图像目标检测方法

目标检测是自动目标识别的一个重要步骤,论文提出了一种自适应的SAR图像目标检测方法,该方法采用基于Weibull分布模型的恒虚警率(CFAR)检测技术,将参考窗口分块,判断各子块类型,根据各子块类型不同,自适应选择参考样本确定阈值。在检测过程中,利用灰度和方差特征,预先排除明显不为目标的像素。对CFAR检测结果,利用目标基本形状特征排除虚警。实验证明,该方法在同质区和非同质区背景下都具有较好的检测性能。     

Simulation and verification of associative processor arrays

This work is based on the design of a VLSI processor array comprising single bit processing elements combined with Content Addressable Memory (CAM) [1,2]. The processors are connected in a linear array with 64 currently being combined on a chip. Each processor is linked to 64 bits of data CAM and 4 bits of subset CAM (used for marking subsets of the array for subsequent processing). The architecture is targeted at image applications including pixel based processing as well as higher level symbolic manipulation and incorporates a data shift register linking all of the processing elements which allows data loading and processing to occur concurrently.

The current situation is that an extensive functional simulation package has been written [3] which allows algorithms to be coded and executed on a system which comprises an arbitrary number of array chips together with its controlling hardware. This allows algorithms to be investigated, and tuned to the architecture. A reduced design has been fabricated and the chips are undergoing parametric testing. A full version of the processor array chip will then be produced allowing a complete image system to be tested.

The VLSI design work undertaken so far [2] shows that the blocks which constitute the design can easily be replicated an arbitrary number of times (subject to chip size constraints) to create an application specific CAM array. The need for this type of flexibility has been borne out by the algorithmic work that has been carried out by a number of workers. In order to make the design of application specific arrays possible it is vital that the simulation tools are fast enough to allow adequate testing to be performed on the new design. It is for this reason that the original simulation package, written in C, has been transferred onto a transputer array.

This paper looks at the way in which the simulation is mapped onto the transputers in such a way that an arbitrary number can be used. In addition the problems of verification and validation of the simulator and the VLSI design are addressed. Results are given for a number of different applications which show very encouraging speed-ups. In many ways it has been found that the efficiency with which the simulation can be carried out with a large number of transputers mirrors the efficiency of the processor array in terms of communications overhead.     

Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC

The article demonstrates the usefulness of heterogeneous System on Chip (SoC) devices in smart cameras used in intelligent transportation systems (ITS). In a compact, energy efficient system the following exemplary algorithms were implemented: vehicle queue length estimation, vehicle detection, vehicle counting and speed estimation (using multiple virtual detection lines), as well as vehicle type (local binary features and SVM classifier) and colour (k-means classifier and YCbCr colourspace analysis) recognition. The solution exploits the hardware–software architecture, i.e. the combination of reconfigurable resources and the efficient ARM processor. Most of the modules were implemented in hardware, using Verilog HDL, taking full advantage of the possible parallelization and pipeline, which allowed to obtain real-time image processing. The ARM processor is responsible for executing some parts of the algorithm, i.e. high-level image processing and analysis, as well as for communication with the external systems (e.g. traffic lights controllers). The demonstrated results indicate that modern SoC systems are a very interesting platform for advanced ITS systems and other advanced embedded image processing, analysis and recognition applications.     

Efficient algorithms for large-scale temporal aggregation

The ability to model time-varying natures is essential to many database applications such as data warehousing and mining. However, the temporal aspects provide many unique characteristics and challenges for query processing and optimization. Among the challenges is computing temporal aggregates, which is complicated by having to compute temporal grouping. We introduce a variety of temporal aggregation algorithms that overcome major drawbacks of previous work. First, for small-scale aggregations, both the worst-case and average-case processing time have been improved significantly. Second, for large-scale aggregations, the proposed algorithms can deal with a database that is substantially larger than the size of available memory. Third, the parallel algorithm designed on a shared-nothing architecture achieves scalable performance by delivering nearly linear scale-up and speed-up, even at the presence of data skew. The contributions made in this paper are particularly important because the rate of increase in database size and response time requirements has out-paced advancements in processor and mass storage technology.     

机场跑道异物监测雷达的杂波图恒虚警率检测

随天线扫描平稳变化的强地杂波是实现机场跑道异物(FOD)检测的主要干扰,传统的空域恒虚警率(CFAR)处理不能有效地检测到目标,针对上述问题,提出了一种单元平均杂波图恒虚警率检测算法。首先基于系统特性和跑道环境建立了回波信号模型;然后通过杂波图划分、单元平均、递归滤波等处理技术,实现了距离—方位二维恒虚警率检测;最后进一步分析影响检测性能的主要参数。仿真结果表明,所提算法在低信杂比背景下能有效检测到弱目标,并获得较高的检测概率。     

雷达恒虚警检测系统仿真

恒虚警(CFAR)处理技术对常采用机载下视或类似工作条件的PD雷达进行目标检测非常重要,文章首先对恒虚警检测原理进行论述,重点讨论单元平均CA-CFAR,最大选择GO(greatest of)-CFAR和最小选择SO(smallest of)-CFAR这三种均值类恒虚警处理方法,建立其数学模型.接下来对接收机噪声信号进行模拟,同时建立目标信号模型,并将所产生的噪声信号与目标信号相叠加仿真雷达系统的接收信号,注入所建立的恒虚警模型中进行检测仿真,给出仿真结果的分析,试验证明了仿真系统的有效性.     

舰载雷达环境下CFAR模块的设计与实现

在舰载雷达目标检测系统中,回波中的杂波与噪声严重影响了系统的检测性能,为此设计了基于FPGA的抗恶劣环境舰载雷达(CFAR)模块.该模块采用抗多目标干扰能力优良的GO-CFAR处理方式,通过数据处理、流水处理排序以及数据流调节等方法加以实现.该模块与传统的恒虚警检测器相比,明显地改善了系统的稳定性和检测性能.     

A New Ship Target Detection Algorithm based on SVMin High Resolution SAR Images

The characteristics of ocean background and target in the high resolution synthetic aperture radar (SAR) images are analyzed.Aiming at the requirements of ship detection in high-resolution synthetic aperture radar (SAR) image,the detection accuracy,intelligence level,real-time and processing efficiency,we put forward a high resolution SAR images ship detection algorithm based on support vector machine.The algorithm designs a pre-training support vector machine (SVM) classifier and complete the screening of the ship target block area,then the algorithm of optimal entropy thresholds proposed by Kapur,Sahoo,Wong(KSW) will be used on the target area selected for fine detection of ship targets.In this paper,several commercial satellite data,such as TerraSAR-X,are used to verify the experiment.Comparing with the classical CFAR detection algorithm,Experimental results show that the algorithm can improve the false alarm caused by the speckle noise and ocean clutter background inhomogeneity.At the same time,the detection speed is also increased by 20% to 35%.     

Scheduling image processing tasks in a multilayer system

Multilayer multiprocessor systems are generally employed in real-time applications such as robotics and computer vision. This paper introduces three heuristic algorithms for multiprocessor task scheduling in such systems. In our model, tasks with arbitrary processing times and arbitrary processor requirements are considered. The scheduling aims at minimising completion time of processes in a two-layer system. We employed an effective lower bound (LB) for the problem. Then, we analysed the average performance of the heuristic algorithms by computing the average percentage deviation of each heuristic solution from the LB on a set of randomly generated problems. We have also applied these algorithms for scheduling computer vision tasks running on prototype multilayer architecture. Our computational and empirical results showed that the proposed heuristic algorithms perform well.     

UltraSparc I: a four-issue processor supporting multimedia

UItraSpare I is a second-generation superscalar processor. It is a high performance, highly integrated, four issue superscalar processor based on the Spare Version 9 64-bit RISC architecture. We have extended the core instruction set to include graphics instructions that provide the most common operations related to two dimensional image processing; two- and three-dimensional graphics and image compression algorithms; and parallel operations on pixel data with 8-, 16-, and 32-bit components. Additional, new memory access instructions support the very high bandwidth requirements typical of graphics and multimedia applications     

On implementing motion-based Region of Interest detection on multi-core CELL

Region of Interest (ROI) detection is a well-studied problem in computer vision for applications such as video surveillance and vision-based robotics. ROI detection may be done using background subtraction schemes with change detection and background estimation. When the camera is not static, these schemes will be ineffective and hence there is a need for global motion estimation (GME) to compensate the camera motion. Robust GME algorithms often require high computation power, rendering them unsuitable for real-time, embedded vision applications. In this article, we use a multi-core processor platform – CELL, to meet the computational requirements of the ROI detection system and to explore the feasibility of potential usage of such heterogeneous processor architecture for vision applications. In particular, we analyze the algorithmic components of a typical GME-based ROI detection system and show how to make efficient use of the parallel and vector computation capabilities in the CELL cores for maximizing the gain on speed performance. We have also ported our system on a Sony PS3 system and promising results have been achieved. Based on the study, various design aspects and implementation challenges are discussed which are believed to be useful for future work in porting vision algorithms on multi-core architectures for real-time embedded applications.     

The parallel computation of eigenvalues and eigenvectors of large Hermitian matrices using the AMT DAP 510

The solution of the algebraic eigenvalue problem is an important component of many applications in science and engineering. With the advent of novel architecture machines, much research effort is now being expended in the search for parallel algorithms for the computation of eigensystems which can gainfully exploit the processing power which these machines provide. Among important recent work References 1-4 address the real symmetric eigenproblem in both its dense and sparse forms, Reference 5 treats the unsymmetric eigenproblem, and Reference 6 investigates the solution of the generalized eigenproblem. In this paper two algorithms for the parallel computation of the eigensolution of Hermitian matrices on an array processor are presented. These algorithms are based on the Parallel Orthogonal Transformation algorithm (POT) for the solution of real symmetric matrices[7,8]. POT was developed to exploit the SIMD parallelism supported by array processors such as the AMT DAP 510. The new algorithms use the highly efficient implementation strategies devised for use in POT. The implementations of the algorithms permit the computation of the eigensolution of matrices whose order exceeds the mesh size of the array processor used. A comparison of the efficiency of the two algorithms for the solution of a variety of matrices is given.     

A high speed multi-level-parallel array processor for vision chips

This paper proposes a high speed multi-level-parallel array processor for programmable vision chips.This processor includes 2-D pixel-parallel processing element(PE)array and 1-D row-parallel row processor(RP)array.The two arrays both operate in a single-instruction multiple-data(SIMD)fashion and share a common instruction decoder.The sizes of the arrays are scalable according to dedicated applications.In PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal directions.This connection can help to speed up local operations in low-level image processing.On the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array.The array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED algorithm.The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.     

Flexible VLIW processor based on FPGA for efficient embedded real-time image processing

Modern field programmable gate array (FPGA) chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance VLIW (very long instruction word) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient ILP (instruction-level parallelism) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors to shorten the development cycle, and to use the powerful FPGA resources to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allows exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated using the proposed development cycle. We also realized the rapid prototyping of embedded contactless palmprint extraction on an FPGA Virtex-6 based board for a biometric application and obtained a processing time of 145.6 ms per image. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability.