一种基于存储器故障原语的March测试算法研究

研究高效率的系统故障测试算法,建立有效的嵌入式存储器测试方法,对提高芯片良品率、降低芯片生产成本,具有十分重要的意义.从存储器基本故障原语测试出发,在研究MarchLR算法的基础上,提出March LSC新算法.该算法可测试现实的连接性故障,对目前存储器的单一单元故障及耦合故障覆盖率提升到100%.采用March LSC算法,实现了内建自测试电路(MBIST).仿真实验表明,March LSC算法能很好地测试出嵌入式存储器故障,满足技术要求.研究结果具有重要的应用参考价值.     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

一种适于FPGA芯片的SRAM单元及外围电路设计

静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。     

基于March C-算法的SRAM芯片的SEU失效测试系统

本文为实现SRAM芯片的单粒子翻转故障检测,基于LabVIEW和FPGA设计了一套存储器测试系统：故障监测端基于LabVIEW开发了可视化的测试平台,执行数据的采集、存储及结果分析任务;板卡测试端通过FPGA向参考SRAM和待测SRAM注入基于March C-算法的测试向量,通过NI公司的HSDIO-6548板卡采集两个SRAM的数据,根据其比较结果判定SEU故障是否发生。该系统可以实时监测故障状态及测试进程,并且具有较好的可扩展性。     

源端射频干扰下SRAM的抗扰性分析

目前已有一些在ESD和电磁干扰下存储器行为的表征研究,但对静态随机存取存储器(SRAM)的连续波抗扰度的频率响应特性的研究很少.文章研究了 SRAM在射频电磁干扰下的失效行为与机理.对SRAM芯片进行射频干扰测试发现,SRAM失效行为与其工作模式相关.使用Hspice进行晶体管级仿真.结果表明,SRAM处于数据保持时,...     

大屏幕TFT-LCD显示用Timing Controller的存储器测试

基于March算法的存储器内建自测试电路能够获得很高的故障覆盖率,但在测试小规模的存储器时暴露出了面积相对比较大的缺点.针对大屏幕Timing Controller芯片"龙腾TC1"中4块640×18 bit SRAM"按地址递增顺序连续进行写操作"的工作特点,提出了一种新的存储器内建自测试方法.该方法按照地址递增顺序向存储器施加测试矢量,避免了直接采用March C算法所带来的冗余测试,简化了内建自测试电路,大大减少了由管子的数量和布线带来的面积开销,可达到March C 算法相同的"测试效果".     

嵌入式存储器的内建自测试算法及测试验证

嵌入式存储器的广泛应用使得内建自测试(BIST,Built-In Self-Test)在当前SoC设计中具有重要的作用,本文着重分析比较了几种BIST测试算法,并对嵌入式BIST的体系结构进行了剖析,最后深入研究了MARCH C-算法的实际应用,使用UMC.18SRAM和2PRAM仿真模型对存储器的BIST测试进行了验证,并成功将其应用于一款USB音视频芯片。     

一种测试SRAM失效的新型March算法

随着工艺偏差的日益增加,新的失效机制也在亚100 nm工艺的CMOS电路里出现了,特别是SRAM单元。SRAM单元的故障由晶体管阈值电压Vt差异引起,而Vt差异又是由工艺偏差造成的。对于这类SRAM失效机制,需要把它映射成逻辑故障模型,并为检测出这类故障研究出新的March测试序列。针对这些逻辑故障模型,提出了一种新型的March算法序列;并通过验证,得到了很高的测试覆盖率。     

SoC的存储器Wrapper设计及故障测试

在系统芯片SoC测试中,存储器的可靠性测试是一项非常重要内容.IEEE Std 1500是专门针对嵌入式芯核测试所制定的国际标准,规范了IP核提供者和使用者之间的标准接口.基于此标准完成针对SoC存储器的Wrapper测试壳结构和控制器的设计.以32×8的SRAM为测试对象进行测试验证.结果表明,系统能够准确的诊断出存储器存在故障.     

基于March X算法的SRAM BIST的设计

针对LS-DSP中嵌入的128kb SRAM模块,讨论了基于March X算法的BIST电路的设计.根据SRAM的故障模型和测试算法的故障覆盖率,讨论了测试算法的选择、数据背景的产生:完成了基于March X算法的BIST电路的设计.128kb SRAM BIST电路的规模约为2000门,仅占存储器面积的1.2%,故障覆盖率高于80%.     

An Efficient Built‐in Self‐Test Algorithm for Neighborhood Pattern‐ and Bit‐Line‐Sensitive Faults in High‐Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.     

Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.     

A transparent online memory test for simultaneous detection of functional faults and soft errors in memories

The Transparent Online Memory Test (TOMT) introduced here has been specifically developed for online testing of word-oriented memories with parity or Hamming protection. Careful interleaving of a word-oriented and a bit-oriented test facilitates a fault coverage and a test duration comparable to the widely used March C- algorithm. Unlike similar methods TOMT actively exercises all bit cells in memory within one test period. Hence it not only detects soft errors but also functional faults and reliably prevents fault accumulation. Different variants of the basic TOMT algorithm are investigated in terms of fault coverage and test time. A prototype implementation for SRAM is introduced which-integrated into a standard processor/memory interface-autonomously performs the transparent online memory test. The trade-offs in terms of hardware overhead and memory access delay caused by this system integration are explored.     

New March Tests for Multiport RAM Devices

This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2ⁿ-bit decoder (with column multiplexers for the column addresses) and drivers, and a K-bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST implementation with a modest area overhead that tests these faults and achieves low test application time.     

嵌入式存储器内建自测试的一种新型应用

当今,嵌入式存储器在SoC芯片面积中所占的比例越来越大,成为SoC芯片发展的一个显著特点。由于本身单元密度很高,嵌入式存储器比芯片上面的其它元件更容易造成硅片缺陷,成为影响芯片成品率的一个重要因素。本文对采用MARCH-C算法的嵌入式存储器内建自测试进行了改进,实现了对嵌入式存储器故障的检测和定位,能够准确判断故障地址和故障类型,使嵌入式存储器故障修复更加快捷、准确,同时达到故障覆盖率高、测试时间短的目的。     

An Effective Test and Diagnosis Algorithm for Dual‐Port Memories

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual‐port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual‐port memories.     

Near-optimal tests for classes of write-triggered coupling faults in RAMs

This article is concerned with the detection of write-triggered coupling faults and toggling faults (certain double coupling faults) in n × 1 random-access memories (RAMs), where n is the number of one-bit words in the memory. In an earlier article we showed that any functional test that detects all multiple coupling faults must have a length of at least 2n ² + 3n. Since such a test is prohibitively long, given modern RAM capacities, we study more manageable subclasses of the class of all coupling faults. We show that there exist two hierarchies of fault models corresponding to nested subclasses of toggling faults and coupling faults, respectively, of increasing maximum multiplicities. We then identify optimal or near-optimal tests for two classes of toggling faults and five classes of coupling faults; these tests are of order n or nlog₂ n.This work was supported by the Natural Sciences and Engineering Research Council of Canada under Grants OGP0105567 and OGP0000871, and by the Information Technology Research Centre of Ontario.     

Performance evaluation of a reconfiguration-algorithm for memoryarrays containing clustered faults

Reconfiguration of memory arrays using spare rows and columns is useful for yield-enhancement of memories. This paper presents a reconfiguration algorithm (QRCF) for memories that contain clustered faults. QRCF operates in a branch and bound fashion similar to known optimal algorithms that require exponential time. However, QRCF repairs faults in clusters rather than individually. Since many faults are repaired simultaneously, the execution-time of QRCF does not become prohibitive even for large memories containing many faults. The performance of QRCF is evaluated under a probabilistic model for clustered faults in a memory array. For a special case of the fault model, QRCF solves the reconfiguration problem exactly in polynomial time. In the general case, QRCF produces an optimal solution with high probability. The algorithm is also evaluated through simulation. The performance and execution-time of QRCF on arrays containing clustered faults are compared with other approximation algorithms and with an optimal algorithm. The simulation results show that QRCF outperforms previous approximation algorithms by a wide margin and performs nearly as well as the optimal algorithm with an execution-time that is orders of magnitude less     

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.