Differential fault simulation for sequential circuits

A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of C language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.     

Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

Fault simulation on massively parallel SIMD machines algorithms,implementations and results

Two algorithms for fault simulation of combinational networks on massively parallel SIMD machines are presented. One algorithm uses a variant of the PPSFP [1] approach, while the other uses a mixture of parallel fault simulation [2] and PPSFP [1]. The algorithms have been implemented on the [Thinking Machines Corporation's] Connection Machine [3]. The second algorithm compares very favorably with published results for well known serial algorithms on the ISCAS benchmark circuits [4]. The results indicate that parallel processing could be a valuable tool for accelerating VLSI CAD applications.     

Bridging Faults in Pipelined Circuits

This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and I _ddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.     

Switched-current circuits test using pseudo-random method

A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described in this paper. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Taking into account of the connection between special structural problems and CMOS’s parameters in switched current circuits such as the drain-gate capacitance C _dg , gate-source capacitance C _gs and transconductance g _m., a integrated fault model for testing is constituted. A 6-order switched-current low-pass filter has been tested based on catastrophic and parametric fault models. The technique does not intrude into the actual design of the switched-current blocks, Pseudo-Random sequence generated from existing digital hardware and analogue output pins are not required.     

A Practical Vector Restoration Technique for Large Sequential Circuits

Given a test sequence and a list of faults detected by the sequence, vector restoration techniques extract a minimal subsequence that detects a chosen subset of modeled faults. Vector restoration techniques are useful in static compaction of test sequences and in fault diagnosis. We propose a new vector restoration technique that is a significant improvement over the state of the art in several ways: (1) a sequence of length n can be restored with only O(n log ₂ n) simulations while known approaches require simulation of O(n ²) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. Our new ideas can be used to improve run-times of known static compaction and fault diagnosis methods. We integrated the proposed vector restoration technique into a static test sequence compaction system. Our experiments show that the new restoration technique, as compared to known techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.), is (1) about 2 times faster for the ISCAS benchmark circuits, and (2) 3 to 5 times faster on large, industrial designs. Using the new restoration technique, we successfully processed large industrial designs that could not be handled by earlier techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.) in 2 CPU days.     

Low-voltage,low-power current monitor for deep-submicron testing

An on-chip low-power circuit for both quiescent current I _ddq and transient current I _ddt monitoring is presented. The current monitor performs faster and is significantly smaller than those reported previously. The monitor is designed for low-voltage digital CMOS circuits (1.5V). The same design can be used in the testing of analogue and mixed signal circuits. The effect on the circuit under test performance is negligible. Testing speeds of up to 25MHz can be achieved (including the 4-bit A/D converter, 100MHz without the converter). The monitor has been implemented in 0.5μm and 0.35μm CMOS technology and tested successfully on parallel chains of inverters as circuit under test. Two types of fault (an open fault and a short fault) have been observed. Simulation and experimental results are included and analysed.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

A new DFT methodology for sequential circuits

This paper introduce a new design for testability methodology for sequential circuits based on input/output pin utilization which exploits the possibility of applying test patterns in parallel. The goal is to reduce the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes necessary and sufficient conditions which are easily incorporated in a design system and produce the required implementation. Successful experimental results are presented on benchmark circuits:IC test length is reduced on an average by 44% of full scan.This work is partly supported by research grants from the Natural Sciences and Engineering Research Council of Canada and equipment grants from the Canadian Microelectronics Corporation.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

Parallel-concurrent fault simulation

A new parallel-concurrent fault simulation algorithm based on the partitioning of faults into groups, with the group size equal to the number of bits in the host computer word, is presented. The fault effects of a particular group are evaluated using parallel fault simulation techniques and propagated using concurrent fault simulation techniques. The speed of the algorithm depends on the circuit and on the fault-grouping criterion. An automatic grouping criterion is devised to group faults that are “close” or nearly equivalent. Comparisons to the concurrent, to the deductive, and to the PROOFS fault simulation techniques are performed on a SPARC SLC with 16 MB of memory running UNIX. ISCAS89 benchmark circuits are used for this comparison     

时序电路的模糊化测试生成算法

文章提出的模糊化的时序电路测试生成算法不明确指定故障点的故障值，它将故障值模糊化，并以符号表示。本算法第一阶段通过计算状态线和原始输出端的故障值来寻找测试矢量，通过计算故障点的正常值来 寻找测试矢量对应的故障类型；第二阶段用故障点的正常值作为约束条件计算故障点的另一个测试矢量。与传统的算法不同，它不需要回退和传播的过程。实验结果表明本算法具有较高的故障覆盖率和较少的测试时间。     

Functional versus random test generation for sequential circuits

This article presents a test generation method for sequential circuits based on their synthesis specifications as finite state machines (FSM) and provides comparison with random test generation. The finite state machines are represented by their state transition graph (STG). The test generation method is performed in two phases. The first phase is functional. It generates a test sequence which is one of the shortest input sequences going through all the transitions of the state transition graph machine. This sequence provides a high fault coverage of stuck-at faults on the synthesized circuit compared to a randomly generated test sequence. This fault coverage is very close to the ones of other sequences derived by fault-oriented test generation approaches [9], [10], although these latter sequences are much longer.The trend of the fault coverage curve for different test sequences including progressively the transitions of the test sequence defined in the first phase is similar to the one of the fault coverage curve of a random sequence but for same lengths the first curve gives larger fault coverage. Both curves grow rapidly until a given ratio of faults is detected then continue to grow very slowly exhibiting low efficiency.The second phase of the test generation method is fault-oriented. It uses a fault simulation based approach in order to compute the test sequence for the remaining faults not detected by the first phase. At the end of this phase the test sequence for all the nonredundant faults is derived and, the combinationally redundant faults and the sequentially redundant faults are distinguished.     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.     

Partitioning sequential circuits for pseudoexhaustive testing

In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of our algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits containing up to 5597 gates. Our algorithm is based upon pseudoexhaustive testing methods where fault simulation is not required for test-pattern generation and grading; hence, engineering design time and cost are further reduced     

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. Furthermore, not only the Single Observation Time Test Strategy is supported, but also test patterns with respect to the Multiple Observation Time Test Strategy are generated. However, there are circuits that are hard to test using random pattern sequences, even if these sequences are genetically optimized. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that both a priori time consuming strategies, the symbolic simulation approach and the GA, can be combined at reasonable costs: Tests with higher fault coverages and considerably shorter test sequences than previously presented approaches are obtained.     

Fault simulation using small fault samples

This article emphasizes simulation-based sampling techniques for estimating fault coverage that use small fault samples. Although random testing is considered to be the primary area of application of the technique it is also suitable for estimating the fault coverage of nonrandom tests based on specific fault models. Especially for fault coverages exceeding 95%, it is shown that a precise estimate can be obtained using a fault sample of only 500 faults. The estimation is based on a binomial approximation of the probability density of the sample fault coverage. Using Bayes statistics an estimate is obtained whose accuracy is a linear function of the sample size if the fault coverage approaches 100%. The sample size is independent of the circuit size, thus making fault sampling particularly interesting for the fault simulation of ULSI designs due to the resulting reduction of the time complexity of fault simulation from O(N ₂) to O(N).This work was performed while Dr. Daehn was with the Laboratorium fuer Informationstechnologie at the university of Han- nover, Germany.     

Delay fault simulation of sequential circuits

This article proposes a 7-valued logic appropriate for test generation and fault simulation, in the area of robust tests for gate delay faults, and a straightforward simulation strategy for sequential circuits. It is shown that a purely qualitative logic of robust testing is inadequate for circuits with edge-triggered flip-flops. The relation between the 7-valued logic and the similar logic proposed before by Smith, Schulz et al., and Lin and Reddy are discussed.     

Quietest: A methodology for selecting I DDQ test vectors

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I _DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I _DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I _DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I _DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.