Asynchronous 250-Mb/s optical receivers with integrated detector instandard CMOS technology for optocoupler applications

A high-speed ten-channel optical receiver, integrated in a standard 0.6-μm CMOS technology, is presented. Each data channel consists of a spatially modulated light detector (SML-detector) and a low-offset receiver. The SML detector has a much higher intrinsic bandwidth than a conventional photodiode junction implemented in standard CMOS. One channel of the ten is sacrificed and used as a reference to define the threshold level for the other channels. The optical receiver can handle up to 250 Mb/s of noncoded data (including dc) per channel at 20 μW average light input power (λ=860 nm). Power dissipation per channel is only 4 mW. When combined with appropriate light emitters, a compact and low-cost optocoupler can be obtained with improved speed performance compared to existing optocouplers     

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter

As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in V_T variation due to RDF results in about 5% spread in delay variability for the 65 nm CMOS inverter.     

CMOS电容式湿度传感器特性研究

提出了一种CMOS电容式湿度传感器特性研究方案.研究所用的微电容湿度传感器由标准CMOS工艺结合MEMS 后处理技术加工而成.为了测试湿度传感器的响应时间,设计了一种响应时间测试装置.测试结果表明,该电容式湿度传感 器在相对湿度25％～95％的范围内具有较好的线性度;其回滞在75％RH时达到最大,为2％ RH;该传感器...     

An algorithmic and novel design of a leading zero detector circuit:comparison with logic synthesis

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. We designed a 32 and 64 bit leading zero detector circuit in CMOS and ECL technology. The CMOS version was designed using both: logic synthesis and an algorithmic approach. The algorithmic implementation is compared with the results obtained using modern logic synthesis tools in the same 0.6 μm CMOS technology. The implementation based on an algorithmic approach showed an advantage compared to the results produced by the logic synthesis. ECL implementation of the 64 bit LZD circuit was simulated to perform in under 200 ps for nominal speed     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

Static Phase Offset in a Multiplying Phase Detector

This article analyzes the static phase offset $DeltaPhi_{O}$ of a Gilbert cell phase detector, and attributes the majority of the offset to intrinsic channel transit time. A 6.5 GHz phase detector fabricated in a standard 0.18 $mu{rm m}$ CMOS technology is used for the study. The static phase offset is broken down into layout and intrinsic contributions, and a simple model is used to calculate the intrinsic component. The use of analytical equations for current and intrinsic phase offset results in prediction of the intrinsic static phase offset to within 12% for the current ranges considered. The use of the intrinsic model with extracted parasitics is then shown via analysis, simulation and experimental data to be useful in predicting the phase detector static phase offset. The analysis, confirmed by measurements, indicates the degree to which the static phase offset can be reduced by increasing the tail bias current.      

A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time

In this paper an analog voltage-mode median filter, which operates on a 3 × 3 kernel is presented. The filter is implemented in a 0.35 μm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing, which allows the calculation of the median of signals with the difference in amplitude as small as 10 mV. This feature allows the application of the filter to vision systems with up to 7 bit equivalent resolution. The analytical and statistical analysis of the filter resolution, and analysis of its speed limitations are presented and compared to measurement results. Based on the achieved results, a set of guidelines for the filter design and optimisation is presented.     

Analysis of CMOS Photodiodes. I. Quantum efficiency

An improved one-dimensional (1-D) analysis of the CMOS photodiode has been derived in which the effect of the substrate, which forms a high-low junction with the epitaxial layer, has been included. The analytical solution was verified with numerical simulations based on parameters extracted from a standard 0.35 /spl mu/m CMOS process. Two empirical parameters are suggested to offset the unavoidable inaccuracies in the extracted parameter values. The derived semiempirical expression exhibits a good agreement with the measured spectral response. In Part II of this paper, a three-dimensional (3-D) analysis of lateral photoresponse in CMOS photodiode arrays is presented along with an empirical modeling method utilizing test linear photodiode arrays.     

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodi-ode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.     

Fast acquisition clock and data recovery circuit with low jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.     

Variable supply-voltage scheme for low-power high-speed CMOSdigital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design     

A new hybrid phase detector for reduced lock time and timing jitter of phase-locked loops

This paper presents a new hybrid phase detector called hybrid phase detector that possesses the characteristics of two-XOR linear phase detectors and improved bang–bang binary phase detectors. Phase-locked loops (PLLs) with the proposed hybrid phase detector possess the intrinsic advantage of the low timing jitter of PLLs with a two-XOR phase detector in lock states and the fast locking process of PLLs with an improved bang–bang phase detector. The effectiveness of the proposed phase detector is quantified by comparing the performance of three PLLs with identical loop components except phase detectors implemented in UMC-0.13 μm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 devices models that account for both the parasitics and high-order effects of devices. Simulation results demonstrate that PLLs with the hybrid phase detector has the same lock time as that of the PLL with an improved bang–bang phase detector. The amplitude of the fluctuation of the control voltage of the PLL with the hybrid phase detector is the same as that of the PLL with an improved bang–bang phase detector in the transient region and the same as that of the PLL with a two-XOR phase detector when the lock state is established. The timing jitter of the PLL with the hybrid phase detector is the same as that of the PLL with the two-XOR phase detector in the lock state and is much lower as compared with that of the PLL with the improved bang–bang phase detector.     

一种低功耗高频CMOS峰值检测电路

给出了一个低功耗、高频CMOS峰值检测电路,可以用于检测射频信号和基带信号的峰值.该电路的设计基于中芯国际0.35μm标准CMOS工艺.理论分析和后仿真结果都表明,在工艺偏差以及温度变化条件下,当输入信号幅度在400mV以上时检测的误差小于2%,检测带宽可达10GHz以上,整个检测电路的静态电流消耗低于20μA.     

An Overview of Analog Feedback Part I: Basic Theory

This two part paper addresses the genuinely difficult problem of efficiently analyzing and designing high performance analog feedback networks. Part I focuses on theoretical considerations and is therefore independent of device technology. Part II exploits the results formulated in Part I to develop models, computationally efficient analytical methods, and design criteria for six types of commonly used feedback architectures. The utility of these models, methods, and criteria is applicable to monolithic bipolar junction transistor, MOS, CMOS, and other device technologies. Part I specifically overviews the traditional mathematics that underlie the study of the circuit transfer, driving point impedance, and frequency response characteristics of analog feedback networks. This review establishes a foundation for developing a computationally efficient form of signal flow theory that embellishes these analytical methods and illuminates design-oriented insights that are otherwise obscured by the tedium pervasive to traditional analyses. The new form of classical signal flow theory, which is a hybrid of signal flow and two-port network theories, is introduced in Part I and developed fully in Part II. This hybrid method of feedback circuit analysis allows for an efficient assessment of the gain, bandwidth, sensitivity, stability, and input/output impedance characteristics of a broad variety of global feedback loops. Additionally, the method complements the task of formulating engineering design guidelines for feedback network design by highlighting the attributes and limitations implicit to specific types of feedback configurations.     

Figures of merit to characterize the importance of on-chipinductance

A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-μm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect     

Analysis of CMOS Photodiodes. II. Lateral photoresponse

For pt.I see ibid., vol.50, no.5, p.1233-38 (2003). In Part I of this paper, an improved one-dimensional (1-D) analysis and a semiempirical model of quantum efficiency for CMOS photodiode was illustrated. In this part of the paper, the lateral photoresponse in CMOS photodiode arrays is investigated with test linear photodiode arrays and numerical device simulations. It is shown that the surface recombination and mobility degradation along the Si-SiO/sub 2/ interface are important factors in determining the lateral photoresponse of CMOS photodiodes. The limitations of traditional analytical approaches are briefly discussed in this context, and a novel three-dimensional (3-D) analysis of lateral photoresponse is presented. Given the significant dependence of lateral photoresponse on the Si-SiO/sub 2/ interface quality, an empirical characterization method is proposed as a more reliable solution to modeling lateral photoresponse.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

一种新型的高速时钟数据恢复电路的设计和验证

针对高速(Gbit/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作。和传统的双环路结构相比,在功耗和面积可比拟的前提下,该结构系统的复杂度低、响应速度快。电路采用1.8 V,0.18μm CMOS工艺流片验证,测试结果显示在2 Gbit/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据。芯片面积约0.5 mm~2,时钟数据恢复部分功耗为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps。