Integrated optical receiver with beam localisation

The performance of optical receivers is degraded by misalignment and defocusing of the incident light beam on a detector. The presented integrated optical receiver solves the alignment and defocusing problem using optoelectronic light beam localisation. A demonstrator is realised in a standard CMOS technology     

Experimental characterization of integrated optical wireless components

Line of sight optical links can provide extremely high bandwidth communications between terminals, but in order to maintain alignment between transmitter and receiver, tracking is required. In this letter, we report results from a "solid-state" tracking transmitter and receiver. The transmitter consists of a custom complementary metal-oxide-semiconductor (CMOS) integrated circuit that is flip-chip bonded to a seven-element resonant cavity light-emitting diode. The receiver uses a custom seven-element InGaAs detector array that is flip-chip bonded to a CMOS integrated circuit. Results from an initial link demonstration show overall system operation at 100 Mb/s/channel, for Manchester coded data.     

An approach to the optical interconnect made in standard CMOS process

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide,metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.     

A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

10Gbit／sX4小型可插拔并行光收发模块的研制

研制了一款基于系统级封装技术的低成本、收发一体和可带电热插拔的4通道小型可插拔（QSFP）光模块,采用850nm垂直腔面发射激光器（VCSEL）阵列及其驱动器作为发射端,光电探测器（PD）阵列及其跨阻放大器（TIA）作为接收端,通过光路无源对准,实现了低成本光互连。高速度、高密度封装下的瞬态同步开关噪声、芯片间电磁干扰...     

光收发器中光电集成接收芯片的实现

针对应用于850nm光通信中的10/100Mbit/s收发器,提出采用0.5μm标准CMOS工艺对其光接收芯片实现Si基单片集成。整体芯片面积为0.6mm2,共集成了一个双光电二极管的(DPD)光电探测器和一个跨阻前置放大电路,功耗为100mW,并给出了具体的测试性能结果。结果表明,在850nm光照下,光接收芯片带宽达到53MHz,工作速率为72Mbit/s。重点介绍了DPD光电探测器的原理和结构,并给出了相应的制造过程和电路等效模型,对整个光接收芯片进行了多种实用性测试,可以满足系统的性能要求。     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of −19.7 dBm to obtain a bit-error rate (BER) of 10⁻¹². The complete receiver consumes a total power of approximately 155 mW from a 3.3-V supply. The core circuit area is 0.85×1.32 mm².     

1Gb/s CMOS调节型共源共栅光接收机

基于特许0.35μm EEPROM CMOS标准工艺设计了一种单片集成光接收机芯片,集成了双光电探测器(DPD)、调节型共源共栅(RGC)跨阻前置放大器(TIA)、三级限幅放大器(LA,limiting amplifier)和输出电路,其中RGCTIA能够隔离光电二极管的电容影响,并可以有效地扩展光接收机的带宽。测试结果表明,光接收机的3dB带宽为821MHz,在误码率为10-9、灵敏度为-11dBm的条件下,光接收机的数据传输速率达到了1Gb/s;在3.3V电压下工作,芯片的功耗为54mW。     

High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector

We present a high-speed monolithically integrated optical receiver fabricated with 0.13-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10^-12 at the incident optical power of - 5.5 dBm.     

Synchronous optical detection unmasked

In this article we presented a new silicon optoelectronic receiver in standard CMOS for synchronous detection of light. Two versions were implemented in a 0.7-μm N-well CMOS technology and tested. In the better version, the light-sensitive junctions were the drains of NMOSFETs. This version operated at up to 180 MHz with external 830-nm light pulses of 176 fJ. Our new receiver shows an excellent trade-off between small size, high speed, and good sensitivity, and is therefore an interesting candidate for applications such as digital optical information transfer between VLSI circuits     

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifierfor an optical receiver, fabricated it in several different minimumfeature sizes of standard digital CMOS, and demonstrated designscaleability of this analog integrated circuit design. The sameamplifier was fabricated in a 1.2 µm and two different0.8 µm processes through the MOSIS foundry [1].The amplifier uses a multi-stage, low-gain-per-stage approach.It has a total of 5 identical cascaded stages. Each stage isessentially a current mirror with a current gain of 3. Threeof these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with anInGaAs MSM detector by using a thin-film epilayer device separationand bonding technology [2]. This quasi-monolithic front-end of anoptical receiver virtually eliminates the parasitics between thephotodetector and the silicon CMOS preamplifier. We have demonstratedspeed and power dissipation improvement as the minimum feature sizeof the transistors shrink.     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

High-speed, highly sensitive OEIC using clocked vertical BJT'sphotoDarlington in CMOS technology

A novel CMOS synchronized photoreceiver is proposed for conversion of optical input pulses to digital output signals. The photoreceiver circuit consists of a photoDarlington used as a detector of input light followed by a current-mirror comparator used as a converter to electronic signals. A combination of two p-n-p vertical CMOS bipolar junction transistors controlled by an external clock is designed to achieve the first clocked photoDarlington structure. The generated photocurrent is amplified and digitized by the current-mirror comparator in a return to-zero format. The synchronized photoreceiver has been implemented in a standard digital 0.7 μm, 5 V n-well CMOS technology with an effective area of 100×60 μm². It was measured to operate at 100 MHz with an external input light of 13.3 fJ/pulse (-18.8 dBm/beam)     

A 256-element CMOS imaging receiver for free-space optical communication

This paper describes a CMOS imaging receiver for free-space optical (FSO) communication. The die contains 256 optical receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range at 500 kb/s/channel while consuming 67 mW. Received signals are amplified by digitally self-calibrated open-loop amplifiers and digitized before clock and data recovery. The sampled data also provide inputs for digital automatic gain and offset control loops closed around the analog amplifier chain to compensate for signal variations due to atmospheric turbulence and daylight interference. Gain control logic can adapt to incident signals over the 30 dB dynamic range within 28 bit periods. Low-power logic design and analog circuit techniques are used to minimize digital crosstalk to single-ended photodetectors referenced to a bulk substrate. Local arbitration circuitry at each channel forms an intrachip data passing network to multiplex received data words from the 16 /spl times/ 16 array onto a common off-chip bus. The 1.6 M transistor mixed-signal die fabricated in a 0.25 /spl mu/m CMOS process measures 6.5/spl times/6.5 mm/sup 2/. Reception at 500 kb/s through a 1.5 km atmospheric channel is demonstrated with 3 mW optical transmit power during nighttime and daylight hours.     

A single-chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems

In this paper, a new fully integrated detector architecture for pick-up units in optical storage systems is presented. It features a special high-frequency photodiode constellation for data recovery suitable for the needs of future optical storage systems. The functionality of standard detectors has been extended by using an additional 5 /spl times/ 5 low-frequency photodiode matrix for in-situ determination of the average spatial light power distribution across the detector. The six high-frequency paths exhibit bandwidths up to 135 MHz, and the maximum clock frequency for the low-frequency paths is 20 MHz. The detector has been fabricated in a standard 0.6-/spl mu/m CMOS process, and it operates at a 3.3-V power supply and occupies 1.78 /spl times/ 1.58 mm/sup 2/.     

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.     

Smart-Optical Detector CMOS Array for Biochemical Parameters Analysis in Physiological Fluids

This paper describes the implementation of a smart-optical detector array for detection and concentration measurement of biochemical parameters in physiological fluids. Its application is in the low-cost microchip size analytical laboratories that use colorimetric detection, by optical absorption, as the analytical technique. The microlaboratory structure is composed of a microplate cuvette array containing the physiological fluids into analysis and an optical detector array underneath, which quantifies the light absorbed by those fluids. The detectors, together with their analog-to-digital (A/D) conversion, are designed and fabricated using a standard CMOS process. The on-chip A/D conversion is performed, simultaneously, using a 1-b first-order sigma–delta converter for each optical detector. The output signal of the device is a bit stream containing information about the absorbed light, which allows simple microcontroller interfacing. The proposed architecture has the main advantage of performing the simultaneous measurement of the light absorbed by the fluids, which avoids the errors that can be introduced due to light fluctuations in uncontrolled environments. In addition, the architecture allows on-chip calibration during each measurement. This means that the device can be reliably used in environments with noncalibrated light sources, e.g., in a doctor's office. The A/D conversion design described here represents significant improvements when compared with the existing designs. Moreover, the microlaboratory application holds great promise, by both improving benefits (quality of health services provided) and reducing costs (of physiological fluid analysis services).