Long-term electron leakage mechanisms through ONO interpoly dielectric in stacked-gate EEPROM cells

Analyzing the measured shift rate of cell threshold-voltage, we have studied the long-term electron leakage mechanisms through an oxide-nitride-oxide (ONO) interpoly dielectric, which causes reliability problems due to the degradation of the data retention characteristics in the stacked-gate Flash EEPROM devices. The cell threshold-voltage shifts were measured as a function of bake time at various temperatures by the high-temperature accelerated test. Based on the experimental results, a new empirical model was developed and evaluated. It can explain the dominant mechanisms for the spontaneous charge leakage through an ONO interpoly dielectric for the long-term phase. The model clearly shows that cell threshold-voltage shifts during the baking test are caused predominantly by the thermally activated direct-tunneling when electrons, after escaping from the internitride trap-sites near the top oxide of ONO layer by the thermionic emission mechanism, finally tunnel through the thin top oxide to the control gate. This interpretation is strongly supported by the V/sub T/-shift and temperature dependence of the V/sub T/-shift rate, showing that the simulation results are well fit to the experimental data.     

A highly robust process integration with scaled ONO interpolydielectrics for embedded nonvolatile memory applications

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides     

Development and application of the Oxide Stress Separation technique for the measurement of ONO leakage currents at low electric fields in 40 nm floating gate embedded-flash memory

The silicon dioxide/silicon nitride/silicon dioxide (ONO) inter-gate dielectric layer has long been used in floating gate flash memories to provide coupling with the control gate, while simultaneously blocking leakage to it. Given the thickness and quality of the ONO, it is not possible to directly measure the leakage currents at low electric fields. This article presents the Oxide Stress Separation (OSS) technique which places a flash cell in a condition where the potential drop occurs entirely across the ONO. This allows for the measurement of currents on the order of 10^− 23 A to be measured at low electric fields using nominal floating gate flash memory cells. Using OSS, state-of-the-art 40 nm embedded-flash memories are characterized, allowing an evaluation of data retention contributors. Comparing OSS results with bake tests, ONO is found to be minimally responsible for the data retention drift, even in modern memories.     

A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO₂ tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.     

Reliability improvement of EEPROM by using WSi2 polycide gate

Recent technology fabrication of EEPROM developed by STMicroelectronics involves tungsten-based polycide for the gate of the transistors. The EEPROM design is based on one floating gate. The main objective was to increase the data retention capability on product using this polycide, and this after cycling. Thus, we have set up a new process called integrated process involving a cluster tool which avoids any contamination during the manufacturing of the polycide stacked layers in comparison with the standard process. In addition, the tungsten chemistry induces an insertion of fluorine in the tunnel oxide. The presence of the fluorine is verified and can explain the modification of the threshold voltages and the evolution of the programming window. Analyses of test cells and product vehicles were made. This new process improves the data retention capability of the EEPROM after one million cycles, and also decreases the cumulative percentage of defects; these results were good enough to insert this process in the production line.     

Polyoxide thinning limitation and superior ONO interpoly dielectricfor nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate     

Si-H bond breaking induced retention degradation during packaging process of 256 mbit DRAMs with negative wordline bias

Data retention degradation of a 256-Mbit DRAM during the packaging process is investigated in this paper. Electrical measurement and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250/spl deg/C. Retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature, but less sensitive to the substrate bias. Trap-assisted gate induced drain leakage is proposed as the mechanism of retention loss in the degraded chip. The degraded chips usually can be repaired by another thermal baking process. We propose Si-H bond breaking and the subsequent trap generation at the gate and drain overlap region as the root cause of retention degradation according to the fact that the Si-H bond density of backend passivation oxide and nitride layers correlate well with the retention performance of DRAM chips with negative wordline bias. Moreover, the packaged chip shows variable retention behavior during a thermal baking of 250/spl deg/C. Theoretical calculation indicates that the trap generation or movement to the high electrical field region beneath the gate can increase the trap-assisted gate induced drain leakage by about an order of magnitude.     

Statistical simulations for flash memory reliability analysis and prediction

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V/sub T/) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements.     

Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices

A theoretical model is developed to characterise the write, erase and charge retention mechanisms of floating gate EEPROM devices. The model depicts the effect of the properties of thin tunnel oxide, interpoly oxide, injector area, and programming voltage on the device performance. The effect of trapping of electrons in the thin oxide during repeated write/erase cycles is also described.     

Hafnium silicate as control oxide in non-volatile memories

SONOS-type MIS capacitors with hafnium silicate as a control oxide are characterized and compared to devices featuring a conventional SONOS gate stack. Write operation is comparable for both gate stack types. Erase operation for the devices with hafnium silicate is improved since the parasitic injection of electrons from the gate is suppressed due to the low electric field in the high-k material. This reduction in leakage current through the gate enhances oxide stability. However, measurements indicate that charge retention for the gate stack with hafnium silicate is degraded for high charge densities. Band bending of the control oxide under high electric fields increases the tunneling probability for trapped charges. Additionally, initial flatband voltage decay is observed due to charge trapping in the hafnium silicate layer. Reducing the thickness of the hafnium silicate layer is possible, maintaining favorable erase properties while minimizing the charge decay rate during retention.     

Numerical analysis of deep-trap behaviors on retention time distribution of DRAMs with negative wordline bias

The data retention time characteristics of the DRAM cell with the negative wordline bias are investigated. With the unique characteristics shown in the gate-induced drain leakage current and the data retention time distribution of the 256-Mb DRAM chip, a model for the sensitivity of data retention time to gate bias is proposed. With the help of two-dimensional device simulation, we found that the relative trap energy (/spl Delta/E/sub t/) of the trap energy to intrinsic Fermi energy plays a key role to determine the retention time of a DRAM cell transistor for the weak cell as well as the normal cell. Also, it is shown the localized trap in the specific region having large electric field is responsible for abnormally large leakage current of the weak cell. An analytic formula for activation energy for the weak cell and the normal cell are also proposed to estimate trap energy level in real device.     

Transient Performance Estimation of Charge Plasma Based Negative Capacitance Junctionless Tunnel FET

We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n⁺ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.     

A true single-transistor oxide-nitride-oxide EEPROM device

A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 Å are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.     

浮栅隧道氧化层EEPROM中浮栅上电荷泄漏研究

本文从研究不同单元尺寸浮栅隧道氧化层EEPROM在不同状态、不同温度保存下阈值电压的变化入手,论述了浮栅隧道氧化层EEPROM中浮栅上电荷的泄漏机理,并提出了改进EEPROM保持特性的措施.     

EEPROM单元的电荷保持特性

利用理论推导和实验方法对电可擦除可编程只读存储器EEPROM单元在给定电压下的电荷保持特性进行了分析和研究,得出了EEPROM单元电荷保持能力的理论公式,得到了单元保持状态下的电特性曲线,发现在双对数坐标下,阈值电压的退化率与时间成线性关系.在假定电荷流失机制为Fowler-Nordheim隧穿效应的情况下,推出了EEPROM单元在给定外加电压下的电荷保持时间,并通过实验得出了简化的EEPROM单元寿命公式.     

Evaluation of layered tunnel barrier charge trapping devices for embedded non-volatile memories

This paper presents experimental results on band gap engineered charge trapping devices for embedded non-volatile memories. Different material systems with high-k dielectrics and metal gates were fabricated using 193 nm lithography and the electrical evaluation was performed on 256 bits mini-arrays. The structure relies essentially on a layered tunnel ONO (oxide-nitride-oxide) barrier that replaces the tunnel oxide in conventional SONOS devices. In addition, we have implemented high-k dielectrics, metal gates and sealing layer in order to achieve low programming voltage and improve the data retention especially at elevated temperature. Whereas, high-k and metal gate systems allow low programme/erase voltages attractive for embedded non-volatile memories, the conventional band gap engineered SONOS (BE-SONOS) offers better high-temperature data retention. However, compared to a SONOS device with a standard “thick” tunnel oxide of 6 nm close to the EOT of the layered tunnel ONO barrier, it appears that BE-SONOS memories suffer from charge loss toward the channel and therefore we believe that the band gap engineered feature of the ONO barrier requires alternative materials.     

An investigation of erase-mode dependent hole trapping in flashEEPROM memory cell

Hot-hole generation during electrical erase in flash memory cells was investigated and found to be strongly dependent on the lateral electric field of the gated diode junction. It is shown, by erasing the memory cell at a low source voltage in combination with a negative gate voltage, that the operating point can be chosen well away from the onset of avalanche. Using this erasing scheme appreciably reduces the amount of hole trapping in the tunnel oxide. As a result, data retention is significantly improved as compared with conventional erasure     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low