A Real-Time Video Decoder for Digital HDTV

In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.     

HDTV接收系统中视频解码的研究与实现

本文简要分析了HDTV接收系统中视频解码的特点与实现方法,介绍了一种HDTV视频解码器的硬件结构及其工作过程。重点讨论了该视频解码器的软件系统结构,主要模块的设计与实现。该视频解码器可对符合MPEG-2 MP@HL的视频流进行解码并兼容多种视频格式的输出。     

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications

In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm² silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory     

高清视频解码中SDRAM控制器的实现

介绍SDRAM在HDTV（1920x1080）视频解码中的应用,提出了在HDTV视频解码系统中实现多模块共享存储单元的高效SDRAM控制器。通过优化控制器的状态机,读写地址合理映射,最终实现高速高效地完成实时视频解码。     

高清电视音频解码算法研究与实现

针对DVB的高清电视音频解码中的子带综合滤波算法进行了改进,使得运算量和存储量都下降了一半以上,采用改进算法的解码器在完成C语言仿真的基础上,进行了浮点程序的定点化改造,以实现基于定点DSP的实时解码,此解码器对高清电视信源解码等众多方面有着广泛的应用.     

基于Cache的HEVC运动补偿带宽优化设计

作为计算量最多的模块之一,运动补偿占用了解码器与片外数据存储器之间约70%的带宽,是实现超高清视频解码的瓶颈。通过所设计的基于Cache的HEVC运动补偿模块,在保证实时解码数据吞吐量的同时,有效减少了80%的带宽消耗。首先,利用由可复用滤波器构成的插值计算模块和2D Cache设计了可并行化流水线数据处理的运动补偿模块,满足计算过程中高数据吞吐量需求。其次,设计高效内部存储器RAM结构,并提出片内Cache功耗降低的有效解决方案。最后,利用了参考帧数据相关性,设计插值顺序重排,将Cache的硬件开销减少了87.5%。基于HM9.0的HEVC标准测试视频序列实验结构表明,该设计显著地减少了带宽消耗和硬件开销。     

高清晰度电视视频解码器码流分配电路实时实现技术

我国自行研制的第一代高清晰度电视功能样机视频编、解码器中,采用十字划分方案,以便使用标准清晰度电视视频编、解码芯片实现高清晰度电视视频编、解码器。文中在介绍高清晰度电视视频码流结构的基础上,提出了高清晰度电视视频解码器中码流分配电路的实现方法,并给出了实现结果。实验表明,使用该方法可以实现码流中头信息的修改、码字划分及不定长视频包的有序传输及控制。     

高清晰度电视芯片中视频和音频同步的异步实现

高清晰度电视的传输流采用了MPEG－2系统层标准ISO／IEC 13818－1。阐述了高清晰度电视（HDTV）传送流中时间信息码在视频和音频同步中的作用，分析了信源解码器中视频和音频同步的原理。就实际芯片中系统时钟的恢复，视频和音频的跳帧等机制进行了讨论，并提出了一种非锁相异步全数字视音同步实现方案。该方案采用了直接置数法恢复系统时钟,滞后跳帧法实现视频与系统时钟的同步，数字锁相法控制音频与系统时钟同步，最后，对视频帧率和音频PCM时钟的偏差等问题作了进一步的探讨。     

基于FPGA的数字高清晰度电视视频解码器的设计和实现

本文介绍了一个能实时解码基于MPEG-2的高清晰度电视(HDTV)编码流的视频解码器的设计方案及其实现。在设计中采用大量FPGA以及能实现高速处理的并行处理技术和流水线工作方式,并研究了由并行处理而导致的运动补偿越界等特殊问题的解决途径。论文阐明了解码器的总体结构和各主要电路的组成以及整个解码过程的具体实现。     

一种改进控制逻辑的面积优化高速RS解码器

给出了一个完整的基于时域解码算法的Reed-Solomon解码器流水结构，用来计算错误位置多项式和错误估值多项式的改进欧几里德算法（Modified Euclid Algorthn,MEA）模块，通过寄存器分组并行计算，大大提高了处理速度。同时，该设计优化了MEA模块的控制逻辑，避免了寄存器组之间的物理交换，每一次迭代均可在固定的时钟周期内完成。此外，对解码器中16个有限域常数乘法器进行了特别的门数优化，求错误值部分采用高效的比特并行求逆电路。该解码器适用于HDTV等数字视频系统。     

基于S3C2440的H．264软编解码器实现

H．264编解码器的软件实现是嵌入式应用领域的热门研究课题。在此介绍以S3C2440为硬件平台,在Linux开发环境下实现基于H．264的x264编码、ffmpeg解码以及ffplay解码播放的移植过程和方法。实验结果表明,在qcif分辨率下,可以获得近实时的解码和播放。最后针对视频流进行实时编解码和播放的要求,提出对编解码优化的方案。     

HDTV中MPEG-2实时解码器的错误处理实用新算法研究

论述了国内外高清晰度数字电视中的ＭＰＥＧ－２实时解码器的错误处理的研究现状及其典型算法,提出了错误处理实用新算法的研究思路。算法研究与ＨＤＴＶ视频解码器硬件研制紧密结合,为国家重大项目－ＨＤＴＶ功能能样机研制直接提供算法支持。     

HDTV集成解码芯片的一种总线设计

本文给出了HDTV集成解码芯片的一种总线设计方案。通过分割总线时间片静态调度DMA传输，并将部分HDTV解码同步控制嵌入到总线调度中，使总线数据传输与解码流程相配合，有效地分配和使用总线带宽，在确保满足系统实时处理性能的条件下，尽可能降低系统对总线带宽的需求，减少片内数据缓冲区容量以降低系统硬件开销。     

Wyner–Ziv-based bidirectionally decodable video coding

In this paper, we propose a novel Wyner–Ziv-based video compression scheme which supports encoding a new type of inter frame called ‘M-frame’. Different from traditional multi-hypothesis inter frames, the M-frame is specially compressed with its two neighbor frames as reference at the encoder, but can be identically reconstructed by using any one of them as prediction at the decoder. Based on this, the proposed Wyner–Ziv-based bidirectionally decodable video compression scheme supports decoding the frames in a video stream in both temporal order and reverse order. Unlike the other schemes which support reverse playback, our scheme achieves the reversibility with low extra cost of storage and bandwidth. In error-resilient test, our scheme outperforms H.264 based schemes up to 3.5 dB at same bit rate. The proposed scheme also provides more flexibility for stream switching.     

Low-power data transfer and storage exploration for H.263 videodecoder system

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data-transfer scheme in the specification, and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst case mode using predicted (P) frames, memory power consumption is reduced by a factor of 7 when compared to the reference design. For the worst case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment     

基于CUDA的多路高清视频流解码器设计与实现

针对多视频流解码和显示时CPU占用率过高等问题。设计了基于统一计算设备架构(CUDA)平台上的GPU多视频流并行化处理方案,定义了表示GPU显卡设备和解码器的数据结构,通过解码函数接口的调用可适用于多种视频播放器中去。实验结果表明,所设计的解码器大幅降低了多视频解码显示中CPU的占用率,同时与JM实现的软件解码方案相比,解码单路720 p的高清视频CPU占用率同比降低约30%,所以此硬件解码方案表现出更加高效的多视频流解码处理能力。提高了系统性能和资源复用率,并能保持较低的能量消耗。     

Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format

The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. While implementing software based video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource synchronization for multiple parallel units. The same applies for hardware implementations of video decoders where monolithic approaches anticipate scalability of the design and reusability of already implemented core components.In this paper, we propose an intermediate data stream format (Meta Format Stream) which is suited for architectural decomposition of video decoding by replacing the conventional monolithic decoder architecture design with a pipelined structure. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264/AVC multiprocessing proposal is presented as a case study for the potential our our concept. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage.The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution.     

Platform-independent MB-based AVS video standard implementation

AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization.     

用于HDTV视频解码器的高性能SDRAM控制器

该文提出了一种适用于HDTV视频解码器的高性能SDRAM控制器。通过为SDRAM控制器设置多个端口并集成仲裁功能,该SDRAM控制器可以取代传统的总线＋DMA结构,为解码器中的功能单元有效地分配存储器的带宽资源。该文提出的SDRAM控制器内建流水线式的地址和数据路径,配合SDRAM本身流水处理指令的特性,能够无延时地处理各个端口上的存储器访问请求,从而降低了对片上缓存的需求。仿真综合结果表明,该文设计的SDRAM控制器满足HDTV解码的性能要求,且与总线＋DMA结构相比,片上缓存容量减少了约70%。     

HDTV解码器同步系统研究

本文讨论了在HDTV信源解码器系统中视频缓冲器的管理，深人研究了HDTV解码器中的同步系统的解决方案，在我国HDTV信源解码样机中用FPGA实现取得了较满意的效果。为设计我国具有知识产权的HDTV及HDTV的ASIC设计提供了重要的参考。