延迟优化的统一可编程互连电路设计和实现

本文设计了一种对可编程逻辑单元CLB和可编程输出单元IOB均具有统一结构的可编程互连电路。通过偏移互连线和回线技术,使得同种可编程互连线的负载分布均匀,保证了可编程逻辑器件FPGA芯片中信号传输的可预测性和规整性;同时,设计过程中对编程点和驱动器电路进行专门的优化设计,减少了5%延时。运用该互连电路到实例FPGA芯片--FDP芯片中,流片后实测数据表明：该可编程互连电路中各种互连线功能正确,可以正确地完成各种信号的互连,整个芯片的延迟统一而且可预测。     

基于FPGA的WALLACE TREE乘法器设计

为了使基于FPGA设计的信号处理系统具有更高运行速度和具有更优化的电路版图布局布线,提出了一种适用于FPGA结构的改进型WALLACE TREE架构乘法器。首先讨论了基于标准单元3∶2压缩器的改进型6∶4压缩器,根据FPGA中slice的结构特点通过在FPGA Editer软件工具编辑,对该压缩器进行逻辑优化,将其应用于FPGA的基本单元slice结构中。并对乘法器的其他部分结构优化整合,实现一个资源和性能达到合理平衡,且易于在FPGA中实现的乘法器。实际运行结果表明,该乘法器的关键路径延时小于8.4 ns,使乘法器时钟频率和系统性能都得到很大提高。     

基于FPGA的电机控制器的设计

文中给出了一种基于现场可编程阵列(FPGA)器件的电机控制器设计方案,利用可编程逻辑器件的特点将电机控制所需的逻辑控制单元电路及外围接口电路等集成在一片FPGA中,提高了整个控制器的稳定性和可靠性;同时利用FPGA灵活的编程特点,可实现较复杂的电机控制算法,进而提高了控制性能;另外FPGA具有现场可重构的特性,保证了所设计的电机控制模块具有良好的可维护性,也大大方便了系统的设计和调试。     

双输出FPGA基本逻辑单元结构的布局布线影响研究

FPGA基本逻辑单元结构对其性能有着巨大的影响.采用实验的方法,基于三种不同的FPGA内基本逻辑单元(BLE)结构,分别对一系列的基准电路进行装箱和布局布线,研究了不同BLE结构对FPGA布局布线性能的影响.研究揭示了不同BLE结构对布局质量,布局、布线延时和面积有较大的影响,BLE_C结构在布局、布线延时和面积上有较好的优化效果.实验结果对FPGA的结构设计以及相应EDA工具的设计具有参考意义.     

基于C语言的半规整电路版图编译器的开发

讨论了和Ｃ语言描述半规整电路版图结构的基本方法,总结出由基本单元拼接出更大单元的基本步骤,形成了较为通用的半规整电路版图编译器的编制方法。采用这一方法,在设计好某一特定类型半规整电路电路的单元版图和整体结构中以比较方便快速地构造出其对庆的版图编码器     

SOC中Data-Path布图设计面临的挑战

目前所设计的系统级芯片(SOC)包含有多个data-path模块,这使得data-path成为整个G大规模集成电路(GSI)设计中最关键的部分.以往的布图理论及算法在许多方面已不能满足data-path布图设计的需要,这主要是由于传统的布图工具没有考虑data-path所特有的电路结构特点.Data-path具有规整的位片结构,具有很高的性能指标要求,如对于时延、耦合效应和串扰等性能都有严格的要求.此外,data-path中还存在大量成束状结构的BUS线网.文中提出了data-path布图设计所面临的挑战.从介绍data-path布图的基本问题入手,重点分析了data-path布图设计中的关键技术,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想.     

SOC中Data-Path布图设计面临的挑战

目前所设计的系统级芯片(SOC)包含有多个data-path模块,这使得data-path成为整个G大规模集成电路(GSI)设计中最关键的部分.以往的布图理论及算法在许多方面已不能满足data-path布图设计的需要,这主要是由于传统的布图工具没有考虑data-path所特有的电路结构特点.Data-path具有规整的位片结构,具有很高的性能指标要求,如对于时延、耦合效应和串扰等性能都有严格的要求.此外,data-path中还存在大量成束状结构的BUS线网.文中提出了data-path布图设计所面临的挑战.从介绍data-path布图的基本问题入手,重点分析了data-path布图设计中的关键技术,并在讨论已有研究工作的基础上针对不同的布图阶段提出了可行的技术路线与设想.     

用于Flash型FPGA的电流读出电路

为了提高Flash型FPGA中的Flash开关单元在编程后驱动能力的一致性,基于0.11μm2P8M Flash工艺,设计了一款用于读取Flash开关单元驱动电流的读出电路。该驱动电流的读出电路采用与压控电流源进行多点比较的方式,能够实现对Flash开关单元驱动电流的精确测量,保证了Flash开关单元在编程后阈值电压分布的一致性,为Flash型FPGA的优越的可编程性提供了高精度的延迟参数,将Flash开关单元驱动电流的差异控制在5%之内,满足了Flash型FPGA对Flash开关单元的技术要求。仿真结果表明,在电流为20～40μA的范围内,该驱动电流的读出电路有很高的精度和线性度,读取误差小于1μA。     

基于优化的、层次式的数/模转换器自动综合

本文介绍了一种基于优化的、层次式的Ｄ／Ａ转换器自动综合方法,该方法根据 本性能要求首先确定对各单元电路的性能要求,再由这些性能要求驱动相应的单元电路综合模块进行单元电路的综合。最后采用一个自下而上的过程难证所产生的Ｄ／Ａ转换器的性能,在两个综合欠上,利用多维下降单纯形优化算法进行优化求解。     

VPR在FPGA结构设计中的应用

现场可编程门阵列(FPGA)是一种应用非常广泛,同时结构性很强的电子器件.它是由一些相同的基本电路单元依据一定的规则排列而成,其性能在很大程度上取决于一些关键性结构参数的设置.通过在一典型FPGA芯片中对不同的逻辑电路进行布局布线,得到相应的面积和延时等信息,由此研究、分析FPGA的结构参数与芯片性能之间的关系,并在实验基础上得出了部分结构参数的优化取值范围.     

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This paper describes such an FPGA routing architecture, called the multibit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, compared to conventional FPGA routing architectures, the multibit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall FPGA area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections.     

PITIA: an FPGA for throughput-intensive applications

In this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new architecture, which targets datapath circuits, uses the concepts of wave steering and pipelined interconnects. We discuss the FPGA architecture and show results for performance, power consumption, clock network performance, and routability. Results for some commonly used datapath designs are encouraging with throughputs in the neighborhood of 625MHz in 0.25-/spl mu/m 2.5-V CMOS technology. Results for random benchmark circuits are also shown. We characterize designs according to their Rent's exponents and argue that designs with predominantly local interconnects are the best fit in PITIA. We also show that as technology scales down toward deep submicron, PITIA shows an increasing throughput performance.     

On-Line Fault Resilience Through Gracefully Degradable ASICs

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic reconfigurations are performed dynamically through operation rescheduling and hardware rebinding. Instead of a complete shuffling, the proposed scheme perturbs the original schedule and binding in a systematic fashion. This regularity of the scheme allows well-structured design planning for the controller and the datapath. The underlying microarchitecture supporting such reconfiguration schemes is briefly outlined. Experimental evidence indicates negligible performance and small hardware overheads.     

An efficient logic emulation system

The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution     

一种超小型AES专用处理器的FPGA实现

提出一种基于FPGA的专用处理器设计.它是用于高级加密标准的超小面积设计,支持密钥扩展(现在设计为128位密钥),加密和解密.这个设计采用了完全的8位数据路径宽度,创新的字节替换电路和乘累加器结构,在最小规模的Xilinx Spartan II FPGA芯片XC2S15上实现了一个高级加密标准AES的专用处理器,使用了不到60%的资源.当时钟为70MHz时,可以达到平均加密解密吞吐量2.1Mb/s.主要应用在把低资源占用,低功耗作优先考虑的场合.     

Unifiable scheduling and allocation for minimizing system cycletime

This paper describes a new scheduling and allocation algorithm which optimizes a datapath-controller system for clock cycle time. The cycle time of a VLSI system depends not only on the characteristics of the datapath and controller in isolation but also on the interactions between them. A datapath may impose both arrival time constraints on controller inputs and departure time constraints on controller outputs. Late-arriving controller inputs may be generated by complex datapath functions, such as ALU carry-out, while early-departure controller outputs may be required to control slow datapath units. If the controller is not designed taking into account arrival and departure times, it may unnecessarily put control logic on the critical timing path. Our synthesis heuristic, which can be used in conjunction with other scheduling heuristics, identifies critical interactions between datapath and controller and reallocates/reschedules them to reduce system cycle time during high-level synthesis. Experimental results show that a unifiable scheduling and allocation (USA) can substantially improve system cycle time with only small area penalties     

一种在线时间序列预测的核自适应滤波器向量处理器

针对信息物理融合系统中的在线时间序列预测问题,该文选择计算复杂度低且具有自适应特点的核自适应滤波器(Kernel Adaptive Filter, KAF)方法与FPGA计算系统相结合,提出一种基于FPGA的KAF向量处理器解决思路。通过多路并行、多级流水线技术提高了处理器的计算速度,降低了功耗和计算延迟,并采用微码编程提高了设计的通用性和可扩展性。该文基于该向量处理器实现了经典的KAF方法,实验表明,在满足计算精度要求的前提下,该向量处理器与CPU相比,最高可获得22倍计算速度提升,功耗降为1/139,计算延迟降为1/26。     

A Hardware Acceleration Platform for Digital Holographic Imaging

This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm which transforms an interference pattern captured on a digital image sensor into visible images. Focus in this work is to maximize computational efficiency, and to minimize the external memory transfer overhead, as well as required internal buffering. The paper presents an efficient processing datapath with a fast transpose unit and an interleaved memory storage scheme. The proposed architecture results in a speedup with a factor 3 compared with the traditional column/row approach for calculating the two-dimensional FFT. Memory sharing between the computational units reduces the on-chip memory requirements with over 50%. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom designed FPGA platform and integrated in a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.     

图像边缘检测高速数字滤波器设计与实现研究

简要介绍了图像边缘检测的基本概念,针对其硬件实现的基本模型进行探讨;分析其关键算术单元,采用了多种优化措施并引入了流水线的设计方法以满足高速应用的要求;提出了3种不同的FIR滤波器实现结构;最终完成FPGA和ASIC设计,对不同结构的实现数据进行比较并给出了结论,实现结果表明该设计可以满足高速系统应用场合。     

SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse

As the complexity of designing system-on-chips increases, so does the need to abstract low-level design issues to improve designer productivity. The reuse of previously designed Intellectual Property (IP) modules is a common form of abstraction used to reduce design time. However, different applications typically use a variety of physical interfaces, communication protocols, and global system-level control for IP modules, which complicates design reuse. In this paper, we describe the SIMPPL system model and an abstraction for IP modules, called the computing element (CE), that facilitate the SoC design for both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The CE abstraction decouples the datapath and system-level communication from the application-specific control to promote design reuse by localizing control redesign of IP for new applications. The SIMPPL model facilitates multi-clock domain SoC designs and expedites system integration by defining the intermodule links and communication protocols