Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Silicon-controlled rectifier (SCR) devices are used as local clamping ESD devices. However, conventional designs suffer from slow turn-on, which causes problems in sub 10 ns charged-device model (CDM) protection, especially in deeply scaled technologies. In this paper, a double-well field-effect diode (DWFED) and an improved field-effect diode (FED) are designed to address this challenge. They are fabricated and characterized in 45 nm silicon-on-insulator (SOI) technology and experimentally demonstrated to be suitable for pad-based local clamping under a normal supply voltage (V_dd) range (at or below 1 V) in high-speed applications. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device performance in CDM events. FED’s advantages in improving transient turn-on behavior and reducing DC leakage current are analyzed and compared with the regular SCR and the DWFED. Technology CAD (TCAD) simulations are used to interpret turn-on behavior and guide design. The improved devices may be implemented in a local clamping scheme that expands the ESD design window for advanced technology nodes.     

ESD protection strategies in advanced CMOS SOI ICs

This paper represents a part of the ESREF 2007 tutorial on the design of IC protection circuits built with advanced deep sub-micron CMOS silicon-on-insulator (SOI) technologies. The tutorial covers fundamental aspects of active rail clamp Electrostatic Discharge (ESD) protection approach to meet the human body model (HBM), machine model (MM), and charged device model (CDM) requirements in SOI ICs. The paper focuses on 65 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. It compares pulsed measurement results of SOI MOSFETs and diodes to bulk devices. It also introduces a response surface method (RSM) to optimize device sizes in the ESD networks.     

ESD issues in advanced CMOS bulk and FinFET technologies: Processing,protection devices and circuit strategies

The ESD performance of several CMOS bulk and SOI technologies is reviewed. The ESD area-efficiency of FinFETs is put in relation to bulk and SOI. CMOS bulk technologies have improved over the past generations owing to the possibility of reduced ESD layout dimensions. While having observed It2 values of less than 2 mA/μm² in 130 nm technology, we are able to obtain almost 4 mA/μm² in 45 nm. Downscaling will shift the challenge for a robust ESD design from the ESD protection device in the IO cell to the metal routing and voltage clamping in the supply tree. This will increase cost and effort for ESD protection of modern IC’s in spite of improvement in It2.For FinFET technologies, the influence of device layout, electrical operation modes and processing is discussed. The initially extremely low ESD values of FinFETs have been strongly improved by overall process maturity and added process features. The ESD levels of FinFET technologies are now scalable up to the levels compliant with full IC design constraints. While the area-performance is still about two times lower than in bulk CMOS, it is much better than anticipated earlier.In light of the challenges ahead for technology and circuit applications, the impact on ESD protection strategies is studied. Classical protection approaches are critically examined regarding the latest technology developments and new requirements for IO interface circuits. A switch from bulk to FinFET technology is still regarded as a major disruption for product architecture and thus ESD.     

ESD保护结构中的SCR设计

硅控整流器SCR作为晶闸管常用于功率器件,具有再生性和从高阻态到低阻态切换的能力.因此合理设计的SCR能成为非常高效的ESD保护电路.文章介绍了SCR的基本机制,SCR、MLSCR、LVTSCR和SCR组合保护电路的结构,并介绍了具有更好ESD性能的设计和版图.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. This paper presents a local ESD protection structure based on dynamic triggered SCR and qualifies through TLP and vf-TLP for GO1 = 1 V and GO2 = 1.8 V power domain.     

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.     

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation problems and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.     

0.6μm SOI NMOS器件ESD性能分析及应用

ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...     

SOI集成电路的ESD保护技术研究进展

近年来，随着SOI技术的快速发展，SOI集成电路的ESD保护已成为一个主要的可靠性设计问题。介绍了SOI ESD保护器件方面的最新进展，阐述了在SOI ESD保护器件设计和优化中出现的新问题，并进行了详细的讨论。     

High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation

This paper presents a novel Silicon Controlled Rectifier (SCR) for power line and local I/O ESD protection. The High holding current SCRs (HHI-SCR) exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current can be controlled by specific SCR design. The HHI-SCR is demonstrated in a 0.10 μm-CMOS and in a 0.4 μm-BiCMOS technology. The design is area efficient.     

Application of transient interferometric mapping method for ESD and latch-up analysis

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90 nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90 nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.     

A new multi-finger SCR-based structure for efficient on-chip ESD protection

This paper introduces a new SCR-based (silicon controlled rectifier) structure for on-chip ESD protection. The STMSCR (smart triggered multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR) using an external triggering circuitry that permits switching from a transparency mode to a protection mode as soon as an ESD event is detected. The trigger voltage can be adjusted by design without any impact on the ESD performance. The STMSCR is multi-finger compliant, thus allowing area-efficient design of pad-located ESD protection. The STMSCR is demonstrated in a 0.18 μm CMOS technology without any process customization; an HBM failure threshold over 115 V/μm is reached while always ensuring current uniformity in multi-finger structures.     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。     

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.     

基于SCR的全芯片ESD保护设计

随着集成电路特征尺寸的减小,集成电路对ESD的要求越来越高,同时集成电路面积和引脚数量的增加,使得全芯片的ESD保护成为挑战。SCR器件相对于其他器件,具有相同面积下最高的ESD保护性能。文章以SCR保护器件为基础,介绍一种新型的ESD保护架构——ESD总线。从全模式和混合电压芯片的ESD保护出发,进而提出了全芯片ESD保护结构,针对现代集成电路芯片引脚不断增多的特点,以及系统集成带来的多电压模式问题,提出了使用ESD总线结构的保护方案来实现全芯片的ESD保护。     

SCR器件在CMOS静电保护电路中的应用

静电放电(ESD)对CMOS电路的可靠性构成了很大威胁。随着CMOS电路集成度的不断提高，其对ESD保护的要求也更加严格。针对近年来SCR器件更加广泛地被采用到CMOS静电保护电路中的情况，文章总结了SCR保护电路发展过程中各种电路的工作机理。旨在为集成电路设计人员提供ESD保护方面的设计思路以及努力方向。     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

Characteristics of ESD protection devices operated under elevated temperatures

In this paper, characteristics of electrostatic discharge (ESD) protection devices operating under ESD stress and various ambient temperatures are investigated. The devices considered are a P +/NW diode and several silicon controlled rectifiers (SCRs) including Lateral SCR (LSCR), Modified Lateral SCR (MLSCR), No Snapback SCR (NS-SCR), Low Voltage Triggering SCR (LVTSCR), and P-Substrate Triggered SCR (PSTSCR) fabricated in a 0.35 μm BCD (Bipolar-CMOS-DMOS) technology. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) tester and the Signatone S1060 heating module, and the TLP I–V characteristics are analyzed in details. TCAD simulation is carried out and underlying physical mechanisms related to the effect of temperature on key ESD parameters are provided.     

Design and characterization of ESD solutions with EMC robustness for automotive applications

Electrostatic discharge (ESD) protection design and characterization with consideration of harmful electromagnetic compatibility (EMC) events for automotive interface networks are presented. The EMC events discussed in this paper include: electrostatic discharge (ESD), electrical fast transient (EFT), surge and automotive environment transients. Key electrical parameters defined in those standards are extracted and compared. To provide efficient protection against these EMC requirements, two major automotive process technologies namely, full-dielectric isolation or silicon on insulator (SOI) and junction isolation (JI), are compared with respect to the leakage current, latch-up immunity, design complexity, EMC handling capability and cost. Protection solutions for EMC-compliance issues are reviewed at both the off-chip and on-chip levels. Trade-offs among several off- and on-chip protection devices with varying degrees of area efficiency and robustness are analyzed.