CCD多晶硅层间绝缘介质对器件可靠性的影响

采用扫描电子显微镜和电学分析技术研究了电荷耦合器件(CCD)多晶硅层间绝缘介质对器件可靠性的影响.研究结果表明,常规热氧化工艺制作的多晶硅介质层,在台阶侧壁存在薄弱区,多晶硅层间击穿电压仅20 V,器件在可靠性试验后容易因多晶硅层间击穿而失效.采用LPCVD淀积二氧化硅技术消除了多晶硅台阶侧壁氧化层薄弱区,其层间击穿电压大于129 V,明显改善了器件可靠性.     

CCD栅介质工艺对多晶硅层间介质的影响

CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响.采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响.研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响.栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大.增加氮化硅氧化时间到320 min,多晶硅层间薄弱区氧化层厚度增加到227 nm.在前一次多晶硅氧化后淀积一层15 nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响.     

LPCVD多晶硅形貌对氧化层击穿特性的影响

多晶硅表面对于电荷耦合器件(CCD)的制作非常重要。采用扫描电子显微镜(SEM)和电学分析技术研究了低压化学气相(LPCVD)法淀积的多晶硅形貌对击穿特性的影响。研究结果表明,减小多晶硅表面颗粒尺寸有助于改善多晶硅氧化层击穿特性。多晶硅氧化层击穿特性与多晶硅和绝缘层交界面的平滑度有关。多晶硅薄膜表面平整度变差,则多晶硅与氧化层之间的界面平滑性变差,多晶硅介质层击穿强度降低。     

TFT晶体管电学测量与耐压性研究

文章用RF—PECVD设备制备了G—SiNx薄膜,研究了TFT器件击穿电压的测定与分析方法,并对成膜条件中的SiH4流量以及G-SiNx膜厚进行浮动变化,以及研究TFT器件击穿电压的变化方式。结果表明：随着SiH4／NH3流量增大,其耐压性降低;增大绝缘膜厚度,耐压性随之增大。文章对TFT耐压性测量方法的探讨以及PECVD工艺条件与耐压性的相关关系的研究。对于制备合格的氮化硅薄膜提供了借鉴与指导。     

n~+多晶硅上热生长SiO_2薄膜的电传导和击穿特性

我们用斜坡电流电压(I-Y)测量方法分析了n~+型无定形淀积多晶硅上热生长SiO_2的传导和击穿特性。结果表明,和在体硅上生长的SiO_2相比,在多晶硅上生长的氧化层(多晶氧化层)的绝缘特性要差一些,这可直接归因于由氧化引起的界面粗糙化——这种界面粗糙化导致了氧化层电场的局域增强。例如,我们在测量中发现,167(?)厚多晶氧化层的击穿电场E_(BD)大约为9.5MV/cm,Fowler—Noodheim隧道效应的有效势垒高度φBeff高达2.78eV,这表明,该厚度的多晶氧化层的性质与体SiO_2是接近的。但是,E_(BD)和φBeff都随着多晶氧化层厚度D_(ox)的增大而逐渐减小。当厚度为165(?)时,E_(BD)近似为2.5MV/cm,而φBeff下降到只有0.83eV。随着D_(ox)的增大,我们发现测出的I-V曲线与外加电压极性的关系越来越密切,这是因为多晶硅/硅界面的氧化诱生界面粗糙化程度比氧化层/多晶硅界面严重,由于Fowler-Noodheim电子注入效应,多层晶硅/硅界面的“导电能力”要高于氧化层/多晶硅界面。 某些器件应用领域要求多晶氧化层具有一定的导电能力,能够通过较大的电流密度而不失效。为此,人们开发了一种多晶硅纹理化方法,对于随后形成的薄多晶氧化物,采用这种方法可减小φBeff,增大击穿电流I_(BD),并可消除I-V曲线对外加偏压极性的依赖关系。该工艺     

薄栅氧化层斜坡电压TDDB击穿参数的研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路的可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。本次实验主要是通过斜坡电压实验来研究薄栅氧化层的TDDB,测出斜坡电压时氧化层的击穿电压、击穿电荷以及击穿时间,研究了斜坡电压情况下,栅氧化层击穿电荷、击穿电压和外加电压斜率等击穿参数间的依赖关系。     

多晶硅部分剥离技术对抗辐照VDMOS动态特性的影响

在考虑VDMOS器件的抗辐照特性时,为了总剂量辐照加固的需求,需要减薄氧化层的厚度,然而,从VDMOS器件的开关特性考虑,希望栅氧化层厚度略大些。本文论证了在保证抗辐照特性的需求的薄氧化层条件下,采用漂移区多晶硅部分剥离技术以器件动态特性的可行性,研究了该结构对器件开启电压、击穿电压、导通电阻、寄生电容、栅电荷等参数的影响,重点研究了漂移区多晶硅窗口尺寸对于VDMOS动态特性的影响。模拟结果显示,选取合理的多晶硅尺寸,可以降低栅电荷Qg,减小了栅-漏电容Cgd,减小器件的开关损耗、提高器件的动态性能。     

含氟超薄栅氧化层的抗击穿特性研究

对含 F超薄栅氧化层的击穿特性进行了实验研究。实验结果表明 ,在栅介质中引入适量的 F可以明显地提高栅介质的抗击穿能力。分析研究表明 ,栅氧化层的击穿主要是由于正电荷的积累造成的 ,F的引入可以对 Si/Si O2 界面和 Si O2 中的 O3 ≡ Si·与 Si3 ≡ Si·等由工艺引入的氧化物陷阱和界面陷阱进行补偿 ,从而减少了初始固定正电荷和 Si/Si O2 界面态 ,提高了栅氧化层的质量。研究结果表明 ,器件的击穿电压与氧化层面积有一定的依赖关系 ,随着栅氧化层面积的减小 ,器件的击穿电压增大。     

SiC JFET功率特性的仿真与优化

建立了常关型SiC结型场效应晶体管(JFET)功率特性的数值模型,研究了不同的结构和材料参数对器件功率特性的影响。仿真结果显示,沟道层、漂移层等各层的厚度及掺杂浓度对器件的开态电阻和击穿电压都有明显的影响;采用电流增强层可以明显提高器件的功率特性。研究结果表明,对SiC JFET的结构参数进行优化,可以有效提高器件的优值(FOM)。     

一种可集成高密度氮氧化硅介质工艺

针对传统二氧化硅、氮化硅等介质材料在制作MOS电容时存在电容密度低、界面特性差的问题,通过对氮离子注入、氮硅氧化实验的分析,成功开发出一种采用注入氮并氧化制作氮氧化硅介质材料的工艺;并使用该工艺研制出与36 V双极工艺兼容、介质的相对介电常数为5.51、击穿电压达81 V、电容密度为0.394 fF/μm²的高密度MOS电容,较传统可集成二氧化硅/氮化硅复合介质电容的电容密度提高了35.86%。该工艺还可用于制作大功率MOSFET的栅介质,可提高器件的可靠性。     

Gate oxide reliabilities in MOS (metal-oxide-semiconductor) structures with Ti-polycide gates

We have investigated the thermal degradation of gate oxide in metal-oxide-semiconductor (MOS) structures with Ti-polycide gates. We found that the Ti-diffusion into the underlying polysilicon and consequently to the gate oxide occurs upon thermal cycling processes, which results in the dielectric breakdown of the gate oxide. We also found that the Ti-diffusion is suppressed by the employment of the thin (about 5 nm) titanium nitride (TiN) diffusion barrier layer, which consequently improved the reliability characterisitics of gate oxide significantly.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Lowering of the breakdown voltage of silicon dioxide by asperities and at spherical electrodes

The paper examines the assumption that asperites and corners in electrodes can be preferential sites for electrical breakdown of silicon dioxide capacitors. It was assumed for this purpose that asperities can be approximated by spherical surfaces, and the breakdown voltage was then calculated at such asperities. Calculations showed that the breakdown voltage of a planar silicon dioxide capacitor can be lowered by one half to two thirds by asperities, when their radius is less than about one half of the oxide thickness. Such a decrease in the breakdown voltage is widely observed in polysilicon oxide capacitors. The effect of asperities is alleviated by a trapped electron charge, which can increase the breakdown voltage significantly. The spherical asperity model accounted for the breakdown voltages observed on a wide range of polysilicon oxide capacitors with oxide thickness varying from 45 to 820 nm. The radius of asperities responsible for breakdown in these experiments was roughly estimated 25–35 nm.     

Junction breakdown instabilities in deep trench isolationstructures

Junction breakdown voltage instability in a p-n junction formed in bulk silicon adjacent to a deep trench filled with polysilicon was investigated. The structure investigated consists of a 5-μm-deep trench filled with heavily p-doped polysilicon. The trench is open at the bottom and is consequently shorted to the p-substrate. The time-dependent behavior of the walkout or the breakdown voltage instability is similar to that reported for planar p-n junctions terminating on surface oxide. Results suggest that trapping of holes in the trench sidewall dielectric is responsible for this phenomenon. The product of trapping center concentration and capture cross section N σ is estimated to be 90 cm^-1     

Determination of the Fowler-Nordheim tunneling barrier from nitride to oxide in oxide:nitride dual dielectric

Using a simple but novel method of analysis, the voltage drop across the oxide (pad-oxide) in the oxide:nitride dual dielectric is determined for both positive and negative gate polarities. From the Fowler-Nordheim plot of the oxide voltage drop, the electron barrier from nitride to oxide is 3.2 ± 0.2 eV. However, the current injection from the nitride electrode is about 7 orders of magnitude lower than the current injection from the silicon electrode under the same oxide field values. This large field-current difference between the two directions of electron injection is consistent with the large difference observed in the J ★ t (charge fluence to breakdown) data.     

Effective improvement of high-k Hf-silicate/silicon interface with thermal nitridation

The electrical properties of polysilicon gate MOS capacitors with hafnium silicate (HfSiO) dielectric, with and without NH/sub 3/ nitridation, were investigated. The results show that with NH/sub 3/ nitridation prior to deposition of HfSiO can effectively tune the flatband voltage close to that of conventional oxide and significantly improve the leakage properties over SiO/sub 2/ (three orders reduction). Furthermore, the excellent interface quality has been evidenced by the result of immunity against soft breakdown with NH/sub 3/ nitridation.     

Characteristics of the NO dielectric film with low pressure chemical vapor deposition in-situ nitridation

We investigated the formation of the thin NO dielectric films by in-situ nitridation of native oxide, and subsequent deposition of silicon nitride in the low pressure chemical vapor deposition systems for the application to the capacitors in high density dynamic random access memory. The native oxide was nitrided at elevated temperatures of 690 or 780°C in the flowing ammonia gas atmosphere, and nitride was deposited by flowing silane gas additionally immediately after the nitridation process. By in-situ nitridation process, we could obtaine 5 and 4.5 nm thick (equivalent oxide thickness) nitride/oxide (NO) dielectric films. These films were characterized to be electrically more reliable than the conventional oxide/nitride/oxide (ONO) films of the same equivalent oxide thickness. The nitrided NO films also showed lower leakage current and higher breakdown voltage than conventional ONO films. We obtained electrically most reliable NO films by loading the wafer at 400°C and nitriding the native oxide at 780°C.     

A method of eliminating B-mode dielectric breakdown failure in gateoxides utilizing a charging phenomenon

An investigation of the dielectric breakdown characteristics of charged samples is discussed. B-mode dielectric breakdown failure was eliminated by scrubbing gate oxide films using a brush. Various scrubbing experiments revealed that this occurred due to charging to a voltage close to the intrinsic breakdown voltage of the gate oxide film. Other characteristics such as C-V curves and time-dependent dielectric breakdown characteristics were not degraded by the charging. The method can be of value in the manufacture of reliable oxide films in ULSI